參數(shù)資料
型號： AD7835AP
廠商： Analog Devices Inc
文件頁數(shù)： 13/28頁
文件大?。?/td> 0K
描述： IC DAC 14BIT QUAD PARA 44-PLCC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時間： 10µs
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 465mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 100k
AD7834/AD7835
Rev. D | Page 20 of 28
MICROPROCESSOR INTERFACING
To load data to the AD7834, PC7 is left low after the first eight
bits are transferred. A second byte of data is then transmitted
serially to the AD7834. Then, a third byte is transmitted and,
when this transfer is complete, the PC7 line is taken high.
AD7834 TO 80C51 INTERFACE
A serial interface between the AD7834 and the 80C51 micro-
controller is shown in Figure 26. TXD of the 80C51 drives SCLK
of the AD7834, while RXD drives the serial data line of the part.
CLR
LDAC
FSYNC
SCLK
DIN
PC5
PC6
PC7
SCK
MOSI
1ADDITIONAL PINS OMITTED FOR CLARITY
AD78341
68HC111
01006-027
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user has to ensure that data in
the SBUF register is arranged correctly so the data is received
MSB first by the AD7834/AD7835. When data is to be trans-
mitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its data in 8-bit
bytes with only eight falling clock edges occurring in the trans-
mit cycle. To load data to the AD7834, P3.3 is left low after the
first 8 bits are transferred. A second byte is then transferred,
with P3.3 still kept low. After the third byte has been trans-
ferred, the P3.3 line is taken high.
Figure 27. AD7834 to 68HC11 Interface
CLR
LDAC
FSYNC
SCLK
DIN
P3.5
P3.4
P3.3
TXD
RXD
1ADDITIONAL PINS OMITTED FOR CLARITY
AD78341
80C511
01006-026
Figure 26. AD7834 to 80C51 Interface
LDAC and CLR on the AD7834 are also controlled by 80C51
port outputs. The user can bring LDAC low after every three
bytes have been transmitted to update the DAC, which has been
programmed. Alternatively, it is possible to wait until all the
input registers have been loaded (12-byte transmits) and then
update the DAC outputs.
AD7834 TO 68HC11 INTERFACE
Figure 27 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7834, while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from Port
Line PC7.
For correct operation of this interface, the 68HC11 should be
configured so that its CPOL bit is 0 and its CPHA bit is 1. When
data is to be transferred to the part, PC7 is taken low. When the
68HC11 is configured like this, data on MOSI is valid on the
falling edge of SCK. The 68HC11 transmits its serial data in 8-bit
bytes, MSB first. The AD7834 also expects the MSB of the 24-bit
write first. Eight falling clock edges occur in the transmit cycle.
In Figure 27, LDAC
CLR
and
are controlled by the PC6 and PC5
port outputs, respectively. As with the 80C51, each DAC of the
AD7834 can be updated after each 3-byte transfer, or all DACs
can be simultaneously updated after 12 bytes are transferred.
AD7834 TO ADSP-2101 INTERFACE
An interface between the AD7834 and the ADSP-2101 is shown
in Figure 28. In the interface shown, SPORT0 is used to transfer
data to the part. SPORT1 is configured for alternate functions.
FO, the flag output on SPORT0, is connected to LDAC and is
used to load the DAC latches. In this way, data is transferred
from the ADSP-2101 to all the input registers in the DAC, and
the DAC latches are updated simultaneously. In the application
shown, the CLR pin on the AD7834 is controlled by circuitry
that monitors the power in the system.
CLR
LDAC
FSYNC
SCLK
DIN
FO
TFS
SCK
DT
1ADDITIONAL PINS OMITTED FOR CLARITY
AD78341
ADSP-21011
POWER
MONITOR
01006-028
Figure 28. AD7834 to ADSP-2101 Interface
The AD7834 requires 24 bits of serial data framed by a single
FSYNC
pulse. It is necessary that this
pulse stay low until
all the data is transferred. This can be provided by the ADSP-2101
in one of two ways. Both require setting the serial word length of
the SPORT to 12 bits, with the following conditions: internal
SCLK, alternate framing mode, and active low framing signal.
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