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參數(shù)資料
| 型號： | AD7840JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT LC2MOS LP 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時間： | 2.5µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 400k |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
AD7840
REV. B
–8–
As in the parallel mode, the LDAC signal controls the loading
of data to the DAC latch. Normally, data is loaded to the DAC
latch on the falling edge of LDAC. However, if LDAC is held
low, then serial data is loaded to the DAC latch on the sixteenth
falling edge of SCLK. If LDAC goes low during the transfer of
serial data to the input latch, no DAC latch update takes place
on the falling edge of LDAC. If LDAC stays low until the serial
transfer is completed, then the update takes place on the six-
teenth falling edge of SCLK. If LDAC returns high before the
serial data transfer is completed, no DAC latch update takes
place. Figure 9 shows the simplified serial input control logic for
the AD7840.
Figure 9. AD7840 Simplified Serial Input Control Logic
AD7840 DYNAMIC SPECIFICATIONS
The AD7840 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as integral and differential nonlinearity. These ac specifications
are required for the signal processing applications such as
speech synthesis, servo control and high speed modems. These
applications require information on the DAC’s effect on the
spectral content of the signal it is creating. Hence, the param-
eters for which the AD7840 is specified include signal-to-noise
ratio, harmonic distortion and peak harmonics. These terms are
discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
DAC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fs/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave out-
put is given by
SNR = (6.02N + 1.76) dB
(1)
where N is the number of bits. Thus for an ideal 14-bit con-
verter, SNR = 86 dB.
Figure 10 shows a typical 2048 point Fast Fourier Transform
(FFT) plot of the AD7840KN with an output frequency of
1 kHz and an update rate of 100 kHz. The SNR obtained from
this graph is 81.8 dB. It should be noted that the harmonics are
taken into account when calculating the SNR.
Figure 10. AD7840 FFT Plot
Effective Number of Bits
The formula given in (1) relates the SNR to the number of bits.
Rewriting the formula, as in (2) it is possible to get a measure of
performance expressed in effective number of bits (N).
N
= SNR 1.76
6.02
(2)
The effective number of bits for a device can be calculated
directly from its measured SNR.
Harmonic Distortion
Harmonic distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7840, total harmonic distortion
(THD) is defined as
THD
= 20 log
V
2
2 +V
3
2 +V
4
2 +V
5
2 +V
6
2
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the 2048-point
FFT plot.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the DAC output
spectrum (up to fs/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
Testing the AD7840
A simplified diagram of the method used to test the dynamic
performance specifications is outlined in Figure 11. Data is
loaded to the AD7840 under control of the microcontroller and
associated logic at a 100 kHz update rate. The output of the
AD7840 is applied to a ninth order, 50 kHz, low-pass filter. The
output of the filter is in turn applied to a 16-bit accurate digi-
tizer. This digitizes the signal and the microcontroller generates
an FFT plot from which the dynamic performance of the
AD7840 can be evaluated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7840JNZ | 制造商:Analog Devices 功能描述:IC 14-BIT DAC |
| AD7840JP | 功能描述:IC DAC 14BIT LC2MOS VOUT 28PLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7840JP-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD7840JPZ | 功能描述:IC DAC 14BIT LC2MOS VOUT 28PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7840JPZ-REEL | 功能描述:IC DAC 14BIT LC2MOS 28PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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