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參數(shù)資料
| 型號： | AD7840JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT LC2MOS LP 24-DIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 15 |
| 設置時間： | 2.5µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 400k |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
AD7840
REV. B
–10–
MICROPROCESSOR INTERFACING
The AD7840 logic architecture allows two interfacing options
for interfacing the part to microprocessor systems. It offers a
14-bit wide parallel format and a serial format. Fast pulse
widths and data setup times allow the AD7840 to interface
directly to most microprocessors including the DSP processors.
Suitable interfaces to various microprocessors are shown in
Figures 15 to 23.
Parallel Interfacing
Figures 15 to 17 show interfaces to the DSP processors, the
ADSP-2100, the TMS32010 and TMS32020. An external
timer controls the updating of the AD7840. Data is loaded to
the AD7840 input latch using the following instructions:
ADSP-2100: DM(DAC) = MR0
TMS32010: OUT DAC,D
TMS32020: OUT DAC,D
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
DAC = AD7840 Address
Figure 15. AD7840–ADSP-2100 Parallel Interface
Figure 16. AD7840–TMS32010 Parallel Interface
Figure 17. AD7840–TMS32020 Parallel Interface
Some applications may require that the updating of the AD7840
DAC latch be controlled by the microprocessor rather than the
external timer. One option (for double-buffered interfacing) is
to decode the AD7840 LDAC from the address bus so that a
write operation to the DAC latch (at a separate address than the
input latch) updates the output. An example of this is shown in
the 8086 interface of Figure 18. Note that connecting the
LDAC
input to the CS input will not load the DAC latch cor-
rectly since both latches cannot he transparent at the same time.
AD7840–8086 Interface
Figure 18 shows an interface between the AD7840 and the 8086
microprocessor. For this interface, the LDAC input is derived
from a decoded address. If the least significant address line, A0,
is decoded then the input latch and the DAC latch can reside at
consecutive addresses. A move instruction loads the input latch
while a second move instruction updates the DAC latch and the
AD7840 output. The move instruction to load a data word
WXYZ to the input latch is as follows:
MOV DAC,#YZWX
DAC = AD7840 Address
Figure 18. AD7840–8086 Parallel Interface
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7840JNZ | 制造商:Analog Devices 功能描述:IC 14-BIT DAC |
| AD7840JP | 功能描述:IC DAC 14BIT LC2MOS VOUT 28PLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7840JP-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD7840JPZ | 功能描述:IC DAC 14BIT LC2MOS VOUT 28PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7840JPZ-REEL | 功能描述:IC DAC 14BIT LC2MOS 28PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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