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參數(shù)資料
| 型號(hào)： | AD7849BR |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14/16BIT SRL-IN 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 143k |
AD7849
Rev. C | Page 12 of 20
t2
t3
t1
t4
t5
t7
DB0
DB15
DB0
DB13
SCLK
SYNC
BIN/COMP
SDIN
(AD7849B/C)
SDIN
(AD7849A)
LDAC, CLR
NOTES
1. DCEN IS TIED PERMANENTLY LOW.
t4
t5
010
08-0
17
Figure 16. Timing Diagram (Standalone Mode)
DIGITAL INTERFACE
The AD7849 contains an input serial-to-parallel shift register and a
DAC latch. A simplified diagram of the input loading circuitry is
shown in Figure 16. Serial data on the SDIN input is loaded to
the input register under control of DCEN, SYNC and SCLK.
When a complete word is held in the shift register, it can then be
loaded into the DAC latch under control of LDAC. Only the data
in the DAC latch determines the analog output on the
.
The daisy-chain enable (DCEN) input is used to select either the
standalone mode or the daisy-chain mode. The loading format
is slightly different depending on which mode is selected.
Serial Data Loading Format (Standalone Mode)
When DCEN is at Logic 0, standalone mode is selected. In this
mode, a low SYNC input provides the frame synchronization
signal that tells the
that valid serial data on the SDIN
input is available for the next 16 falling edges of SCLK. An internal
counter/decoder circuit provides a low gating signal so that only
16 data bits are clocked into the input shift register. After 16 SCLK
pulses, the internal gating signal goes inactive (high), thus locking
out any further clock pulses. Therefore, either a continuous clock
or a burst clock source can be used to clock in data.
The SYNC input is taken high after the complete 16-bit word is
loaded in.
The B version and C version are 16-bit resolution DACs and have a
straight 16-bit load format, with the MSB (DB15) being loaded
first. The A version is a 14-bit DAC; however, the loading structure
is still 16 bit. The MSB (DB13) is loaded first, and the final two
bits of the 16-bit stream must be 0s.
The DAC latch, and hence the analog output, can be updated in
two ways. The status of the LDAC input is examined after SYNC
is taken low. Depending on its status, one of two update modes
is selected.
If LDAC = 0, then automatic update mode is selected. In this mode,
the DAC latch and analog output are updated automatically when
the last bit in the serial data stream is clocked in. The update
thus takes place on the 16th falling SCLK edge.
If LDAC = 1, then automatic update mode is disabled. The DAC
latch update and output update are now separate. The DAC latch is
updated on the falling edge of LDAC. However, the output update
is delayed for a further 5 μs by means of an internal track-and-hold
amplifier in the output stage. This function results in a lower
digital-to-analog glitch impulse at the DAC output. Note that
the LDAC input must be taken back high again before the next
data transfer is initiated.
÷16
COUNTER/
DECODER
RESET EN
GATED
SIGNAL
INPUT
SHIFT REGISTER
(16 BITS)
GATED
SCLK
SDOUT
DCEN
SYNC
SCLK
AUTO-UPDATE
CIRCUITRY
SDIN
DAC LATCH
(14/16 BITS)
LDAC
CLR
0100
8-018
Figure 17. Simplified Loading Structure
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