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參數(shù)資料
| 型號(hào)： | AD7849BR |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14/16BIT SRL-IN 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 143k |
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AD7849
Rev. C | Page 13 of 20
t2
DB0 (N)
DB15
(N + 1)
DB0
(N + 1)
DB0 (N)
DB15 (N)
DB0 (N)
DB13 (N)
DB13
(N + 1)
DB0
(N + 1)
DB0 (N)
DB13 (N)
t6
SCLK
SYNC
BIN/COMP
SDIN
(AD7849B/C)
SDOUT
(AD7849B/C)
SDIN
(AD7849A)
SDOUT
(AD7849A)
LDAC, CLR
NOTES
1. DCEN IS TIED PERMANENTLY HIGH.
t7
DB15 (N)
t6
t1
t3
t4
t5
t4
t5
010
08-
019
Figure 18. Timing Diagram (Daisy-Chain Mode)
Serial Data Loading Format (Daisy-Chain Mode)
By connecting DCEN high, daisy-chain mode is enabled. This
mode of operation is designed for multiDAC systems where
several AD7849s can be connected in cascade. In this mode, the
internal gating circuitry on SCLK is disabled, and a serial data
output facility is enabled. The internal gating signal is permanently
active (low) so that the SCLK signal is continuously applied to
the input shift register when SYNC is low. The data is clocked
into the register on each falling SCLK edge after SYNC goes low. If
more than 16 clock pulses are applied, the data ripples out of the
shift register and appears on the SDOUT line. By connecting this
line to the SDIN input on the next
in the chain, a
multiDAC interface can be constructed. Sixteen SCLK pulses
are required for each DAC in the system. Therefore, the total
number of clock cycles must equal 16 × N, where N is the total
number of devices in the chain. When the serial transfer to all
devices is complete,
SYNC is taken high, which prevents any
further data from being clocked into the input register.
A continuous SCLK source can be used if SYNC is held low for
the correct number of clock cycles. Alternatively, a burst clock
containing the exact number of clock cycles can be used and
SYNC taken high some time later.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC latches with the data in each input
register. All analog outputs are therefore updated simultaneously,
5 μs after the falling edge of LDAC.
Clear Function (CLR)
The clear function bypasses the input shift register and loads
the DAC latch with all 0s. It is activated by taking CLR low. In
all ranges, except the offset binary bipolar range (–5 V to +5 V),
the output voltage is reset to 0 V. In the offset binary bipolar
range, the output is set to VREF–. This clear function is distinct and
separate from the automatic power-on reset feature of the device.
APPLYING THE AD7849
Power Supply Sequencing and Decoupling
If this happens, then an internal diode is turned on, and it produces
latch-up in the device. Care should be taken to employ the
following power supply sequence: VDD, VSS, and then VCC. In
systems where it is possible to have an incorrect power sequence
(for example, if VCC is greater than 0.4 V while VDD is still 0 V),
the circuit shown in Figure 19 can be used to ensure that the
Absolute Maximum Ratings are not exceeded.
SD103C
1N5711
1N5712
1N4148
VDD
VCC
VDD
AD7849
010
08
-02
0
Figure 19. Power Supply Protection
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