- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10272 > AD7854LARZ-REEL (Analog Devices Inc)IC ADC 12BIT PARALLEL LP 28SOIC PDF資料下載
參數(shù)資料
| 型號： | AD7854LARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT PARALLEL LP 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極；1 個偽差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD7854/AD7854L
REV. B
–21–
Self-Calibration Timing
Figure 29 shows the timing for a software full self-calibration.
Here the BUSY line stays high for the full length of the self-
calibration. A self-calibration is initiated by writing to the con-
trol register and setting the STCAL bit to 1. The BUSY line
goes high at the end of the write to the control register, and
BUSY goes low when the full self-calibration is complete after a
time tCAL as show in Figure 29.
t23
DATA LATCHED INTO
CONTROL REGISTER
Hi-Z
DATA
VALID
tCAL
CS
WR
DATA
BUSY
Figure 29. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line is triggered high at the end of the write to the
control register and stays high for the full duration of the self-
calibration. The length of time for which BUSY is high depends
on the type of self-calibration that is initiated. Typical values are
given in Table VIII. The timing diagram for the other self-
calibration options is similar to that outlined in Figure 29.
System Calibration Description
System calibration allows the user to remove system errors
external to the AD7854/AD7854L, as well as remove the errors
of the AD7854/AD7854L itself. The maximum calibration
range for the system offset errors is
±5% of VREF, and for the
system gain errors it is
±2.5% of VREF. If the system offset or
system gain errors are outside these ranges, the system calibration
algorithm reduces the errors as much as the trim range allows.
Figures 30 through 32 illustrate why a specific type of system
calibration might be used. Figure 30 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be removed by a system offset calibration.
MAX SYSTEM OFFSET
IS ±5% OF VREF
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
AGND
VREF + SYS OFFSET
VREF – 1LSB
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
ANALOG
INPUT
RANGE
MAX SYSTEM OFFSET
IS ±5% OF VREF
VREF – 1LSB
SYS OFFSET
AGND
Figure 30. System Offset Calibration
Figure 31 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
AGND
SYS FULL S.
VREF – 1LSB
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS FULL S.
AGND
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
Figure 31. System Gain Calibration
Finally in Figure 32 both the system offset error and gain error
are removed by the system offset followed by a system gain cali-
bration. First the analog input range is shifted upwards by the
positive system offset and then the analog input range is
adjusted at the top end to account for the system full scale.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
MAX SYSTEM OFFSET
IS ±5% OF VREF
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION SYS OFFSET
AGND
VREF + SYS OFFSET
VREF – 1LSB
ANALOG
INPUT
RANGE
MAX SYSTEM OFFSET
IS ±5% OF VREF
VREF – 1LSB
SYS OFFSET
AGND
SYS F.S.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
Figure 32. System (Gain + Offset) Calibration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2418CGN#TRPBF | IC ADC 24BIT DIFF INPUT 28SSOP |
| LTC2418CGN#TR | IC ADC 24BIT DIFF INPUT 28SSOP |
| AD7262BSTZ-5 | IC ADC 2CH 12BIT PGA/COM 48LQFP |
| AD7262BCPZ-5 | IC ADC 2CH 12BIT PGA/COM 48LFCSP |
| LTC2418CGN | IC ADC 24BIT DIFF INPUT 28SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7854LBR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| AD7854SQ | 制造商:Rochester Electronics LLC 功能描述:12-BIT SINGLE CH.PARALLEL ADC I.C. - Bulk |
| AD7856 | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
| AD7856AN | 制造商:Analog Devices 功能描述:ADC Single SAR 285ksps 14-bit Serial 24-Pin PDIP 制造商:Analog Devices 功能描述:IC 14BIT ADC 7856 DIP24 |
| AD7856ANZ | 功能描述:IC ADC 14BIT 8CHAN 5V 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。