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參數(shù)資料
| 型號(hào)： | AD7854LARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 27/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT PARALLEL LP 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極 |
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AD7854/AD7854L
–8–
REV. B
AD7854/AD7854L ON-CHIP REGISTERS
The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7854/AD7854L will operate as a read-only ADC. The
WR pin should be tied to DV
DD for operating the AD7854/AD7854L as a
read-only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and
calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first
8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the
8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each
transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to
determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the
address bits, while Figure 2 shows the overall write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
This combination does not address any register.
0
1
This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.
1
0
This combination addresses the CALIBRATION REGISTER. The 14 least significant data bits are writ-
ten to the selected calibration register.
1
This combination addresses the CONTROL REGISTER. The 14 least significant data bits are written to
the control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. Note: when reading from the calibration registers, the low byte must always be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register
until the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1
RDSLT0
Comment
0
All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-
up setting. There is always four leading zeros when reading from the ADC output data register.
0
1
All successive read operations are from the TEST REGISTER.
1
0
All successive read operations are from the CALIBRATION REGISTERS.
1
All successive read operations are from the STATUS REGISTER.
TEST
REGISTER
CALIBRATION
REGISTERS
CONTROL
REGISTER
ADDR1, ADDR0
DECODE
01
10
11
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
GAIN(1)
CALSLT1, CALSLT0
DECODE
00
01
10
11
Figure 2. Write Register Hierarchy/Address Decoding
TEST
REGISTER
CALIBRATION
REGISTERS
CONTROL
REGISTER
RDSLT1, RDSLT0
DECODE
01
10
11
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
GAIN(1)
CALSLT1, CALSLT0
DECODE
00
01
10
11
ADC OUTPUT
DATA REGISTER
00
Figure 3. Read Register Hierarchy/Address Decoding
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