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參數(shù)資料
| 型號： | AD7865BSZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 4CHAN 5V 44-MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 160mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
REV. B
AD7865
–6–
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
BUSY
Busy Output. The busy output is triggered high by the rising edge of
CONVST and remains
high until conversion is completed on all selected channels.
2
FRSTDATA
First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output
Data Register Pointer is addressing Register 1—See Accessing the Output Data Registers.
3
CONVST
Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds
into their hold mode and starts conversion on the selected channels. In addition, the state of
the Channel Sequence Selection is also latched on the rising edge of
CONVST.
4
CS
Chip Select Input. Active low logic input. The device is selected when this input is active.
5
RD
Read Input. Active low logic input which is used in conjunction with
CS low to enable the
data outputs. Ensure the
WR pin is at logic high while performing a read operation.
6
WR
Write Input. A rising edge on the
WR input, with CS low and RD high, latches the logic state
on DB0 to DB3 into the channel select register.
7
CLK IN/SL1
Conversion Clock Input/Hardware Channel Select. The function of this pin depends upon the
H/S SEL input. When the H/S SEL input is high (choosing software control of the channel
selection sequence), this pin assumes its CLK IN function. CLK IN is an externally applied
clock (that is only necessary when INT/EXT CLK is high) this allows the user to control the
conversion rate of the AD7865. Each conversion needs 16 clock cycles in order for the conver-
sion to be completed. The clock should have a duty cycle that is no greater than 60/40. See
Using an External Clock.
When the
H/S SEL input is low (choosing hardware control of the channel conversion se-
quence), this pin assumes its Hardware Channel Select function. The SL1 input determines
whether Channel 1 is included in the channel conversion sequence. The selection is latched
on the rising edge of
CONVST. See Selecting a Conversion Sequence.
8
INT/EXT CLK/SL2
Internal/External Clock/Hardware Channel Select. The function of this pin depends upon the
H/S SEL input. When the H/S SEL input is high (choosing software control of the channel
selection sequence), this pin assumes its
INT/EXT CLK function. When INT/EXT CLK is at
a Logic 0, the AD7865 uses its internally generated master clock. When
INT/EXT CLK is at
Logic 1, the master clock is generated externally to the device and applied to CLK IN.
When the
H/S SEL input is low (choosing hardware control of the channel conversion sequence),
this pin assumes its Hardware Channel Select function. The SL2 input determines whether
Channel 2 is included in the channel conversion sequence. The selection is latched on the
rising edge of
CONVST. When H/S is at Logic 1 these pins have no function and can be tied
to Logic 1 or Logic 0. See Selecting a Conversion Sequence.
9, 10
SL3, SL4
Hardware Channel Select. When the
H/S SEL input is at Logic 0, the SL3 input determines
whether Channel 3 is included in the channel conversion sequence while SL4 determines
whether Channel 4 is included in the channel conversion sequence. When the pin is at Logic
1, the channel is included in the conversion sequence. When the pin is at Logic 0, the channel
is excluded from the conversion sequence. The selection is latched on the rising edge of
CONVST. See Selecting a Conversion Sequence.
11
H/S SEL
Hardware/Software Select Input. When this pin is at a Logic 0, the AD7865 conversion
sequence selection is controlled via the SL1–SL4 input pins and runs off an internal clock.
When this pin is at Logic 1, the conversion sequence is controlled via the channel select regis-
ter and allows the ADC to run with an internal or external clock. See Selecting a Conversion
Sequence.
12
AGND
Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s
AGND plane.
13–16
VIN4x, VIN3x
Analog Inputs. See Analog Input section.
17
AGND
Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND pin
should be connected to the system’s AGND plane.
18–21
VIN2x, VIN1x
Analog Inputs. See Analog Input section.
22
STBY
Standby Mode Input. This pin is used to put the device into the power save or standby mode.
The
STBY input is high for normal operation and low for standby operation.
23
AGND
Analog Ground. General Analog Ground. This AGND pin should be connected to the
system’s AGND plane.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7865BSZ-3REEL | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7865YS-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| AD7865YS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R |
| AD7865YS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk |
| AD7865YS-3 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP |
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