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參數(shù)資料
| 型號(hào)： | AD7865BSZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 4CHAN 5V 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 160mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)差分，雙極 |
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REV. B
AD7865
–14–
Using an External Clock
With the
H/S SEL and INT/EXT CLK pins tied to Logic 1, the
AD7865 will expect to be driven from an external clock. The
highest external clock frequency allowed is 5 MHz. This means
a conversion time of 3.2
s compared to 2.4 s using the inter-
nal clock. In some instances, however, it may be useful to use an
external clock when high throughput rates are not required. For
example, two or more AD7865s may be synchronized by using
the same external clock for all devices. In this way there is no
latency between output logic signals like
EOC due to differences
in the frequency of the internal clock oscillators. Figure 10
shows how the various logic outputs are synchronized to the CLK
signal. The first falling edge of CLKIN must not occur until
200 ns after a conversion has been initiated (rising edge of
CONVST), at which point BUSY will go high. The AD7865
will then convert the analog input signal on the first selected
channel (see Selecting a Conversion Sequence) at a rate deter-
mined by the CLKIN. No external events will occur until the
14th falling edge of CLKIN. The data register output address
is then reset to point to Data Register 1 and FRSTDATA goes
high. This first conversion is complete on the 15th falling edge
of the CLKIN (indicated by
EOC going low) and the result
from this conversion is loaded into Data Register 1.
EOC goes
high again on the 16th falling edge of CLKIN. Figure 10 shows
a
RD pulse occurring when EOC is low, enabling the conversion
result in Data Register 1 onto the data bus. The next 16 pulses
of CLKIN will convert the analog input signal on the second
selected channel and so on until all selected channels have been
converted. BUSY and
EOC will go low on the 15th falling edge
of the last conversion sequence and
EOC will return high on the
16th falling edge.
Standby Mode Operation
The AD7865 has a Standby Mode whereby the device can be
placed in a low current consumption mode (3
A typ). The
AD7865 is placed in standby by bringing the logic input
STBY
low. The AD7865 can be powered up again for normal opera-
tion by bringing
STBY logic high. The output data buffers are
still operational while the AD7865 is in standby. This means the
user can still continue to access the conversion results while the
AD7865 is in standby. This feature can be used to reduce the
average power consumption in a system using low throughput
rates. To reduce the average power consumption the AD7865 can
be placed in standby at the end of each conversion sequence,
i.e., when BUSY goes low and taken out of standby again prior
to the start of the next conversion sequence. The time it takes
the AD7865 to come out of standby is called the “wake-up”
time. This wake-up time will limit the maximum throughput
rate at which the AD7865 can be operated when powering down
between conversions. The AD7865 will wake up in less than
1
s when using an external reference. When the internal refer-
ence is used, the wake-up time depends on the amount of time
the AD7865 spends in standby mode. For standby times of less
than 10 ms the AD7865 will wake up in less than 5
s (see Fig-
ure 11). For standby times greater than this some or all of the
charge on the external reference capacitor will have leaked away
and the wake-up time will be dependent on how long it takes to
recharge. For standby times less than one second the wake-up
time will be less than 1 ms. Even if the charge has been completely
depleted the wake-up time will typically be less than 10 ms.
STANDBY TIME –
s
0
2500
5000
7500
10000
2.5
5
WAKE-UP
TIME
–
s
Figure 11. Wake-Up Time vs. Standby Time Using the On-
Chip Reference
FIRST CONVERSION
COMPLETE
BUSY
RD
EOC
FRSTDATA
CONVST
CLK
t18
2 34567 89 10 11 12 13 14 15 16 1
23456789 10 11 12 13 14
1
15 16
16
15
LAST CONVERSION
COMPLETE
Figure 10. Using an External Clock
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7865BSZ-3REEL | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7865YS-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| AD7865YS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R |
| AD7865YS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk |
| AD7865YS-3 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP |
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