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參數(shù)資料
| 型號： | AD7880CNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT MONO LOW PWR 24DIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 66k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極 |
AD7880
–6–
REV. 0
The AD7880 has two unipolar input ranges, 0 V to 5 V and 0 V
to 10 V. Figure 5 shows the analog input for the 0 V to 5 V
range. The designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output code is straight binary
with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV. The same applies
for the 0 V to 10 V range, as shown in Figure 6, except that the
LSB size is bigger. In this case 1 LSB = FS/4096 = 10 V/4096 =
2.44 mV. The ideal input/output transfer characteristic for both
these unipolar ranges is shown in Figure 8.
1LSB =
FS
4096
OUTPUT
CODE
0V
111...111
111...110
111...101
111...100
000...011
000...001
000...000
000...010
V
INPUT VOLTAGE
IN
1LSB
FS – 1LSB
+
Figure 8. AD7880 Unipolar Transfer Characteristic
Figure 7 shows the AD7880’s
±5 V bipolar analog input con-
figuration. Once again the designed code transitions occur mid-
way between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 10 V/4096 = 2.44 mV.
The ideal bipolar input/output transfer characteristic is shown in
Figure 9.
FS
–
2
FS = 10V
1LSB =
4096
FS
OUTPUT
CODE
111...111
111...110
100...101
100...000
011...111
011...110
000...001
000...000
FS
+
2
1LSB
–
0V
V INPUT VOLTAGE
IN
1LSB
–
1LSB
+
Figure 9. AD7880 Bipolar Transfer Characteristic
CLOCK INPUT
The AD7880 is specified to operate with a 2.5 MHz clock con-
nected to the CLKIN input pin. This pin may be driven directly
by CMOS or TTL buffers. The mark/space ratio on the clock
can vary from 40/60 to 60/40. As the clock frequency is slowed
down, it can result in slightly degraded accuracy performance.
This is due to leakage effects on the hold capacitor in the inter-
nal track-and-hold amplifier. Figure 10 is a typical plot of accu-
racy versus clock frequency for the ADC.
2.5
2.0
1.5
1.0
0.5
0.0
0.5
1.5
2.5
3.5
CLOCK FREQUENCY – MHz
NORMALIZED
LINEARITY
ERROR
Figure 10. Normalized Linearity Error vs. Clock Frequency
TRACK/HOLD AMPLIFIER
The charge balanced comparator used in the AD7880 for the
A/D conversion provides the user with an inherent track/hold
function. The track/hold amplifier acquires an input signal to
12-bit accuracy in less than 3
s. The overall throughput time is
equal to the conversion time plus the track/hold amplifier acqui-
sition time. For a 2.5 MHz input clock, the throughput time is
15
s.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion, i.e., on the ris-
ing edge of CONVST as shown in Figure 1.
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal range match the maximum possible dynamic range of the
ADC. In such applications, offset and full-scale error will have
to be adjusted to zero.
The following sections describe suggested offset and full-scale
adjustment techniques which rely on adjusting the inherent off-
set of the op amp driving the input to the ADC as well as tweak-
ing an additional external potentiometer as shown in Figure 11.
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