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參數(shù)資料
| 型號： | AD7880CNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT MONO LOW PWR 24DIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 66k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極 |
AD7880
REV. 0
–7–
+
–
V1
R1
10 k
VINA
AGND
AD7880*
R2
500
R3
10 k
R5
10 k
R4
10 k
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. Offset and Full-Scale Adjust Circuit
Unipolar Adjustments
In the case of the 0 V to 5 V unipolar input configuration, unipolar
offset error must be adjusted before full-scale error. Adjustment is
achieved by trimming the offset of the op amp driving the ana-
log input of the AD7880. This is done by applying an input
voltage of 0.61 mV (1/2 LSB) to V1 in Figure 11 and adjusting
the op amp offset voltage until the ADC output code flickers
between 0000 0000 0000 and 0000 0000 0001. For full-scale
adjustment, an input voltage of 4.9982 V (FS–3/2 LSBs) is
applied to V1 and R2 is adjusted until the output code flickers
between 1111 1111 1110 and 1111 1111 1111.
The same procedure is required for the 0 V to 10 V input con-
figuration of Figure 6. An input voltage of 1.22 mV (1/2 LSB) is
applied to V1 in Figure 11 and the op amp’s offset voltage is
adjusted until the ADC output code flickers between 0000 0000
0000 and 0000 0000 0001. For full-scale adjustment, an input
voltage of 9.9963 V (FS–3/2 LSBs) is applied to V1 and R2 is
adjusted until the output code flickers between 1111 1111 1110
and 1111 1111 1111.
Bipolar Adjustments
Bipolar zero and full-scale errors for the bipolar input configura-
tion of Figure 7 are adjusted in a similar fashion to the unipolar
case. Again, bipolar zero error must be adjusted before full-scale
error. Bipolar zero error adjustment is achieved by trimming the
offset of the op amp driving the analog input of the AD7880
while the input voltage is 1/2 LSB below ground. This is done
by applying an input voltage of –1.22 mV (1/2 LSB) to V1 in
Figure 11 and adjusting the op amp offset voltage until the
ADC output code flickers between 0111 1111 1111 and 1000
0000 0000. For full-scale adjustment, an input voltage of
4.9982 V (FS/2–3/2 LSBs) is applied to V1 and R2 is adjusted
until the output code flickers between 1111 1111 1110 and
1111 1111 1111.
DYNAMIC SPECIFICATIONS
The AD7880 is specified and tested for dynamic performance
specifications as well as traditional dc specifications such as
integral and differential nonlinearity. The ac specifications are
required for signal processing applications such as speech recog-
nition, spectrum analysis and high speed modems. These appli-
cations require information on the ADC’s effect on the spectral
content of the input signal. Hence, the parameters for which the
AD7880 is specified include SNR, harmonic distortion, inter-
modulation distortion and peak harmonics. These terms are dis-
cussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by:
SNR = (6.02 N + 1.76) dB
(1)
where N is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input which is
sampled at a 66 kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be ob-
tained. Figure 12 shows a typical 2048 point FFT plot of the
AD7880 with an input signal of 2.5 kHz and a sampling fre-
quency of 61 kHz. The SNR obtained from this graph is 73 dB.
It should be noted that the harmonics are taken into account
when calculating the SNR.
Figure 12. FFT Plot
Effective Number of Bits
The formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
N
=
SNR
1.76
6.02
(2)
The effective number of bits for a device can be calculated
directly from its measured SNR.
Figure 13 shows a plot of effective number of bits versus input
frequency for an AD7880 with a sampling frequency of 61 kHz.
The effective number of bits typically remains better than 11.5
for frequencies up to 12 kHz.
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