AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VRE" />
參數(shù)資料
型號: AD7985BCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大?。?/td> 0K
描述: IC ADC 16B 2.5MSPS PULSR 20LFCSP
標(biāo)準(zhǔn)包裝: 1,500
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 2.5M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 33mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 20-LFCSP-VQ
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個偽差分,單極
AD7985
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = 40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge
to Data Available
tCONV
Turbo mode/normal mode
320/420
ns
Acquisition Time
tACQ
80
ns
Time Between Conversions
tCYC
Turbo mode/normal mode
400/500
ns
CNV Pulse Width
tCNVH
CS mode
10
ns
Data Read During Conversion
tDATA
Turbo mode/normal mode
190/290
ns
Quiet Time During Acquisition from Last SCK
Falling Edge to CNV Rising Edge
tQUIET
20
ns
SCK Period
tSCK
CS mode
9
ns
tSCK
Chain mode
11
ns
SCK Low Time
tSCKL
3.5
ns
SCK High Time
tSCKH
3.5
ns
SCK Falling Edge to Data Remains Valid
tHSDO
2
ns
SCK Falling Edge to Data Valid Delay
tDSDO
4
ns
CNV or SDI Low to SDO D15 MSB Valid
tEN
5
ns
CNV or SDI High or Last SCK Falling Edge
to SDO High Impedance
tDIS
CS mode
8
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
4
ns
SDI Valid Hold Time from CNV Rising Edge
tHSDICNV
CS mode
0
ns
tHSDICNV
Chain mode
0
ns
SCK Valid Setup Time from CNV Rising Edge
tSSCKCNV
Chain mode
5
ns
SCK Valid Hold Time from CNV Rising Edge
tHSCKCNV
Chain mode
5
ns
SDI Valid Setup Time from SCK Falling Edge
tSSDISCK
Chain mode
2
ns
SDI Valid Hold Time from SCK Falling Edge
tHSDISCK
Chain mode
3
ns
SDI High to SDO High
tDSDOSDI
Chain mode with busy indicator
15
ns
1
See Figure 2 and Figure 3 for load conditions.
500A
IOL
500A
IOH
1.4V
TO SDO
CL
20pF
07947-
002
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
10% VIO
VIH1
VIL1
VIH1
tDELAY
1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
07947-
003
Figure 3. Voltage Levels for Timing
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