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| 型號(hào)： | AD7985BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16B 2.5MSPS PULSR 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，單極 |
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AD7985
Rev. A | Page 16 of 28
VOLTAGE REFERENCE INPUT
The AD7985 allows the choice of a very low temperature drift
internal voltage reference, an external reference, or an external
buffered reference.
The internal reference of the AD7985 provides excellent
performance and can be used in almost all applications.
Internal Reference, REF = 4.096 V (PDREF Low)
To use the internal reference, the PDREF input must be low.
This enables the on-chip band gap reference and buffer, result-
ing in a 4.096 V reference on the REF pin (1.2 V on REFIN).
The internal reference is temperature compensated to
4.096 V ± 15 mV. The reference is trimmed to provide
a typical drift of 10 ppm/°C.
The output resistance of REFIN is 6 k when the internal
reference is enabled. It is necessary to decouple this pin with a
ceramic capacitor of at least 100 nF. The output resistance of
REFIN and the decoupling capacitor form an RC filter, which
helps to reduce noise.
Because the output impedance of REFIN is typically 6 k,
relative humidity (among other industrial contaminants) can
directly affect the drift characteristics of the reference. A guard
ring is typically used to reduce the effects of drift under such
circumstances. However, the fine pitch of the AD7985 makes
this difficult to implement. One solution, in these industrial
and other types of applications, is to use a conformal coating,
such as Dow Corning 1-2577 or HumiSeal 1B73.
External 1.2 V Reference and Internal Buffer (PDREF High)
To use an external reference along with the internal buffer, PDREF
must be high. This powers down the internal reference and allows
the 1.2 V reference to be applied to REFIN, producing 4.096 V
(typically) on the REF pin.
External Reference (PDREF High, REFIN Low)
To apply an external reference voltage directly to the REF pin,
PDREF should be tied high and REFIN should be tied low.
BVDD should also be driven to the same potential as REF. For
example, if REF = 2.5 V, BVDD should be tied to 2.5 V.
The advantages of directly using an external voltage reference
are as follows:
SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a larger reference voltage (5 V)
instead of a typical 4.096 V reference when the internal
reference is used. This is calculated by
=
0
.
5
096
.
4
log
20
SNR
Power savings when the internal reference is powered
down (PDREF high).
Reference Decoupling
The AD7985 voltage reference input, REF, has a dynamic input
impedance that requires careful decoupling between the REF
and REFGND pins. The Layout section describes how this can
be done.
When using an external reference, a very low impedance source
(for example, a reference buffer using the AD8031 or the AD8605)
and a 10 F (X5R, 0805 size) ceramic chip capacitor are appro-
priate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For example, a 22 F (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference decoupling capacitor with a value as small
as 2.2 F can be used with minimal impact on performance,
especially DNL.
In any case, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and REFGND pins.
POWER SUPPLY
The AD7985 has four power supply pins: an analog supply
(AVDD), a buffer supply (BVDD), a digital supply (DVDD),
and a digital input/output interface supply (VIO). VIO allows
direct interface with any logic from 1.8 V to 2.7 V. To reduce the
number of supplies needed, VIO, DVDD, and AVDD can be tied
together. The power supplies do not need to be started in a par-
ticular sequence. In addition, the AD7985 is very insensitive to
power supply variations over a wide frequency range.
In normal mode, the AD7985 powers down automatically at
the end of each conversion phase and, therefore, the power
scales linearly with the sampling rate. This makes the part ideal
for low sampling rates (even a few SPS) and battery-powered
applications.
10
1
0.1
0.01
0.1
1
O
P
E
RAT
ING
CURRE
NT
(
mA)
SAMPLING RATE (MSPS)
07947-
121
IBVDD
IAVDD
IDVDD
IVIO
IVREF
Figure 25. Operating Current vs. Sampling Rate in Normal Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7986 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 nV/√Hz, Low Power |
| AD7986BCPZ | 功能描述:IC ADC 18BIT 2MSPS SAR 20LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7986BCPZ-RL7 | 功能描述:IC ADC 18BIT 2MSPS SAR 20LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7986BCPZ-U1 | 制造商:Analog Devices 功能描述:16-BIT, 10MSPS PULSAR DIFFERENTIAL ADC - Rail/Tube |
| AD7986XCPZ-U1 | 制造商:Analog Devices 功能描述:16-BIT, 10MSPS PULSAR DIFFERENTIAL ADC - Rail/Tube |
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