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參數(shù)資料
| 型號： | AD8139ACPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP DIFF R-R LN LDIST 8LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分，滿擺幅 |
| 轉(zhuǎn)換速率： | 800 V/µs |
| -3db帶寬： | 410MHz |
| 電流 - 輸入偏壓： | 2.25µA |
| 電壓 - 輸入偏移： | 150µV |
| 電流 - 電源： | 24.5mA |
| 電流 - 輸出 / 通道： | 100mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 12 V，±2.25 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-VD（3x3） |
| 包裝： | 帶卷 (TR) |
AD8139
Rev. B | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12 V
VOCM
±VS
Power Dissipation
See Figure 4
Input Common-Mode Voltage
±VS
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +125°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
Table 4.
Package Type
θJA
Unit
8-Lead SOIC with EP/4-Layer
70
°C/W
8-Lead LFCSP/4-Layer
70
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic will change its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8139. Exceeding a junction
temperature of 175°C for an extended period can result in
changes in the silicon devices potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes,
ground, and power planes reduce the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP
(θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values
are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
M
A
X
IM
UM
P
O
W
E
R
DI
S
IP
AT
IO
N
(
W
)
SOIC
AND LFCSP
0
46
79
-05
5
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
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