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參數(shù)資料
| 型號： | AD8153-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD8153 |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 主要目的： | 接口，2:1 多路復用器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD8153 |
| 主要屬性： | 單道 3.2Gbps 2:1 多路復用器/1:2 多路分解器開關 |
| 次要屬性： | 16 ps 確定性抖動，500 fs rms 隨機抖動，通過 USB 實現(xiàn) GUI |
| 已供物品： | 板，纜線，CD |
| 產(chǎn)品目錄頁面： | 801 (CN2011-ZH PDF) |
| 相關產(chǎn)品： | AD8153ACPZ-RL7DKR-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP AD8153ACPZ-RL7CT-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP AD8153ACPZ-RL7TR-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP AD8153ACPZ-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP |
AD8153
Rev. 0 | Page 13 of 24
THEORY OF OPERATION
The AD8153 consists of a 2:1 multiplexer and a 1:2 demultiplexer.
There are three operating modes: pin mode, serial mode, and
mixed mode. In pin mode, lane switching, equalization, and
pre-emphasis are controlled using external pins. In serial mode,
an I2C interface is used to control the device and to provide
access to advanced features, such as additional pre-emphasis
settings and output disable. In mixed mode, the user accesses
the advanced features using I2C but controls lane switching
using external pins.
SWITCH CONFIGURATIONS
On the demultiplexer side, the AD8153 relays received data on
Input Port C to Output Port A and/or Output Port B, depending
on the state of the BICAST and SEL bits. On the multiplexer
side, the device relays received data on either Input Port A or Input
Port B to Output Port C, depending on the state of the SEL bit.
When bicast mode is off, the outputs of either Port A or Port B
are in an idle state. In the idle state, the output tail current is set
to 0, and the P and N sides of the lane are pulled up to the output
termination voltage through the on-chip termination resistors.
The device also supports loopback on all ports, illustrated in
Figure 31. Enabling loopback on any port overrides configurations
set by the BICAST and SEL control bits. Table 5 summarizes the
possible switch configurations.
The AD8153 output disable feature can be used to force an
output into the idle (powered-down) state. This feature is only
accessible through the serial control interface.
1:2 DEMUX
2:1 MUX
INPUT C
OUTPUT C
PORT C LOOPLOCK
OUTPUT A
OUTPUT B
INPUT A
INPUT B
PORT A LOOPBACK
PORT B LOOPBACK
06
39
3-
00
3
Figure 31. Loopback Configurations
Table 5. Switch Configurations
LB_A
LB_B
LB_C
SEL
BICAST
Output A
Output B
Output C
0
Input C
Idle
Input A
0
1
Input C
Input A
0
1
0
Idle
Input C
Input B
0
1
Input C
Input B
0
1
0
Input C
Idle
Input C
0
1
X
1
Input C
0
1
0
Idle
Input C
0
1
0
X
Input C
Input B
Input A
0
1
0
1
0
Idle
Input B
0
1
0
1
Input C
Input B
0
1
0
X
Input C
Input B
Input C
0
1
0
Idle
Input B
Input C
0
1
X
1
Input C
Input B
Input C
1
0
Input A
Idle
Input A
1
0
1
Input A
Input C
Input A
1
0
1
X
Input A
Input C
Input B
1
0
1
0
Input A
Idle
Input C
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| AD8155 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6.5 Gbps Dual Buffer Mux/Demux |
| AD8155ACPZ | 功能描述:IC MUX/DEMUX DUAL BUFFER 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:XStream™ 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8155ACPZ-R7 | 功能描述:IC MUX/DEMUX DUAL BUFFER 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:XStream™ 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8155-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6.5 Gbps Dual Buffer Mux/Demux |
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