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參數(shù)資料
| 型號： | AD8153-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD8153 |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 主要目的： | 接口，2:1 多路復用器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD8153 |
| 主要屬性： | 單道 3.2Gbps 2:1 多路復用器/1:2 多路分解器開關 |
| 次要屬性： | 16 ps 確定性抖動，500 fs rms 隨機抖動，通過 USB 實現(xiàn) GUI |
| 已供物品： | 板，纜線，CD |
| 產品目錄頁面： | 801 (CN2011-ZH PDF) |
| 相關產品： | AD8153ACPZ-RL7DKR-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP AD8153ACPZ-RL7CT-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP AD8153ACPZ-RL7TR-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP AD8153ACPZ-ND - IC SW MUX/DEMUX SGL BUFF 32LFCSP |
AD8153
Rev. 0 | Page 15 of 24
I2C SERIAL CONTROL INTERFACE
REGISTER SET
The AD8153 can be controlled in one of three modes: pin
mode, serial mode, and mixed mode. In pin mode, the AD8153
control is derived from the package pins, whereas in serial
mode a set of internal registers controls the AD8153. There is
also a mixed mode where switching is controlled via external
pins, and equalization and pre-emphasis are controlled via the
internal registers. The methods for writing data to and reading
data from the AD8153 are described in the I2C Data Write
section and the I2C Data Read section.
The mode is controlled via the MODE pin. To set the part in
pin mode, MODE should be driven low to VEE. When MODE
is driven high to VCC, the part is set to serial or mixed mode.
In pin mode, all controls are derived from the external pins. In
serial mode, each channel’s equalization and pre-emphasis are
controlled only through the registers, as described in Table 8.
Additionally, further functionality is available in serial mode as
each channel’s output can be enabled/disabled with the Output
Enable control bits, which is not possible in pin mode. To
change the switching in the AD8153 to serial mode, the mask
bits (Register 0x00) must be set to 1 by writing the value 0x1F to
this register, as explained in the following sections. Once all the
mask bits are set to 1, switching is controlled via the LB_A,
LB_B, LB_C, SEL, and BICAST bits in the register set.
In mixed mode, each channel’s equalization and pre-emphasis
are controlled through the registers as described above. The
switching, however, can be controlled using either the external
pins or the internal register set. The source of the control is
selected using the mask bits (Register 0x00). If a mask bit is set
to 0, the external pin acts as the source for that specific control.
If a mask bit is set to 1, the associated internal register acts as
the source for that specific control. As an example, if Register 0x00
were set to the value 0x0C, the SEL and LB_C controls would
come from the internal register set (Bit 0 of Register 0x04 and Bit
3 of Register 0x03, respectively), and the BICAST, LB_A, and
LB_B controls would come from the external pins.
GENERAL FUNCTIONALITY
The AD8153 register set is controlled through a 2-wire I2C
interface. The AD8153 acts only as an I2C slave device. Therefore,
the I2C bus in the system needs to include an I2C master to
configure the AD8153 and other I2C devices that may be on the
bus. When the MODE pin is set to a Logic 1, data transfers are
controlled through the use of the two I2C wires: the input clock
pin, SCL, and the bidirectional data pin, SDA.
The AD8153 I2C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to only
toggle when the SDA line is stable unless indicating a start,
repeated start, or stop condition.
Table 8. Register Map
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
00000000
(0x00)
BICAST MASK
SEL MASK
LB_C MASK
LB_B MASK
LB_A MASK
00000000
(0x00)
00000001
(0x01)
OUTPUT DISABLE A
LB_A
EQ_A
PE_A [1]
PE_A [0]
00000000
(0x00)
00000010
(0x02)
OUTPUT DISABLE B
LB_B
EQ_B
PE_B [1]
PE_B [0]
00000000
(0x00)
00000011
(0x03)
OUTPUT DISABLE C
LB_C
EQ_C
PE_C [1]
PE_C [0]
00000000
(0x00)
0000100
(0x04)
BICAST
SEL
00000000
(0x00)
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