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參數(shù)資料
型號(hào): AD8220BRMZ-R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 11/28頁(yè)
文件大小: 0K
描述: IC AMP INST JFET R-R 15MA 8MSOP
產(chǎn)品培訓(xùn)模塊: Power Line Monitoring
設(shè)計(jì)資源: Fully Isolated Input Module Based on AD7793, ADuM5401, and a High Performance In-Amp (CN0067)
標(biāo)準(zhǔn)包裝: 1,000
放大器類型: 儀表
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 2 V/µs
-3db帶寬: 1.5MHz
電流 - 輸入偏壓: 10pA
電壓 - 輸入偏移: 125µV
電流 - 電源: 750µA
電流 - 輸出 / 通道: 15mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 36 V,±2.25 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
AD8220
Rev. B | Page 19 of 28
THEORY OF OPERATION
Q2
Q1
NODE A
NODE B
NODE C
NODE D
VB
C1
C2
A1
A2
–VS
+VS
–VS
J1
+IN
VPINCH
+VS
–VS
J2
–IN
VPINCH
+VS
–VS
RG
+VS
–VS
20k
+VS
–VS
+VS
–VS
REF
OUTPUT
A3
NODE E
NODE F
I
R2
24.7k
R1
24.7k
03
57
9-
00
6
Figure 55. Simplified Schematic
The AD8220 is a JFET input, monolithic instrumentation amplifier
based on the classic 3-op amp topology (see Figure 55). Input
Transistor J1 and Input Transistor J2 are biased at a fixed current so
that any input signal forces the output voltages of A1 and A2 to
change accordingly; the input signal creates a current through RG
that flows in R1 and R2 such that the outputs of A1 and A2 provide
the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2,
and R2 can be viewed as precision current feedback amplifiers that
have a gain bandwidth of 1.5 MHz. The common-mode voltage
and amplified differential signal from A1 and A2 are applied to a
difference amplifier that rejects the common-mode voltage but
amplifies the differential signal. The difference amplifier employs
20 kΩ laser-trimmed resistors that result in an in-amp with gain
error less than 0.04%. New trim techniques were developed to
ensure that CMRR exceeds 86 dB (G = 1).
Using JFET transistors, the AD8220 offers an extremely high
input impedance, extremely low bias currents of 10 pA
maximum, a low offset current of 0.6 pA maximum, and no
input bias current noise. In addition, input offset is less than
125 μV and drift is less than 5 μV/°C. Ease of use and robustness
were considered. A common problem for instrumentation
amplifiers is that at high gains, when the input is overdriven,1
an excessive milliampere input bias current can result and the
output can undergo phase reversal. The AD8220 has none of
these problems; its input bias current is limited to less than
10 μA, and the output does not phase reverse under overdrive
fault conditions.
1 Overdriving the input at high gains refers to when the input signal is within
the supply voltages but the amplifier cannot output the gained signal. For
example, at a gain of 100, driving the amplifier with 10 V on ±15 V constitutes
overdriving the inputs since the amplifier cannot output 100 V.
The AD8220 has extremely low load-induced nonlinearity. All
amplifiers that comprise the AD8220 have rail-to-rail output
capability for enhanced dynamic range. The input of the AD8220
can amplify signals with wide common-mode voltages even
slightly lower than the negative supply rail. The AD8220 operates
over a wide supply voltage range. It can operate from either a
single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The
transfer function of the AD8220 is
G
R
G
49.4
1
Users can easily and accurately set the gain using a single,
standard resistor. Because the input amplifiers employ a current
feedback architecture, the AD8220 gain-bandwidth product
increases with gain, resulting in a system that does not suffer as
much bandwidth loss as voltage feedback architectures at higher
gains. A unique pinout enables the AD8220 to meet a CMRR
specification of 80 dB through 5 kHz (G = 1). The balanced
pinout, shown in Figure 56, reduces parasitics that adversely
affect CMRR performance. In addition, the new pinout
simplifies board layout because associated traces are grouped
together. For example, the gain setting resistor pins are adjacent
to the inputs, and the reference pin is next to the output.
TOP VIEW
(Not to Scale)
03
57
9-
00
5
–IN
1
RG 2
RG 3
+IN
4
+VS
8
VOUT
7
REF
6
–VS
5
AD8220
Figure 56. Pin Configuration
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