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參數(shù)資料
型號(hào)： AD8304ARU-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 10/20頁
文件大?。?/td> 0K
描述： IC LOGARITHMIC CONV 14-TSSOP T/R
設(shè)計(jì)資源： Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056)
Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
標(biāo)準(zhǔn)包裝： 1,000
類型： 對(duì)數(shù)轉(zhuǎn)換器
應(yīng)用： 光纖
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
REV. A
–18–
AD8304
1
VNEG
ACOM 14
2
PWDN
BFNG 13
3
VSUM
VPS1 12
4
INPT
VOUT 11
5
VSUM
VPS2 10
6
VPDB
BFIN
9
7
VREF
VLOG
8
C2
1nF
C1
0.1nF
R10
10k
+VS
–VS
GND
SW1
R5
OPEN
R7
OPEN
LK1
INSTALLED
INPUT
BIASER
LK2 OPEN
C10
0.1 F
C11
1nF
R15
750
R7
OPEN
R9
0.1 F
R6
OPEN
C9
10nF
R4
OPEN
R3
OPEN
R1
OPEN
R2
0
C3
1nF
C4
0.1 F
R11
0
R14
0
C6
OPEN
C5
OPEN
C7
OPEN
R12
OPEN
C8
OPEN
R13
0
BUFFER
OUT
LOG
OUT
AD8304
Figure 22. Evaluation Board Schematic
AD8138
EVALUATION
BOARD
OUTPUT INPUT INPUTA
HP 3577A
NETWORK
ANALYZER
INPUTB
+IN
B
A
VNEG
PWDN
VSUM
INPT
VSUM
VPDB
VREF
ACOM
BFNG
VPS1
VOUT
VPS2
BFIN
VLOG
1
2
3
4
5
6
7
14
13
12
11
10
9
8
POWER
SPLITTER
0.1 F
R1
750
1nF
+VS
AD8304
Figure 20. Configuration for Logarithmic
Amplifier Bandwidth Measurement
The setup shown in Figure 20 was used for frequency response
measurements of the logarithmic amplifier section. In this con-
figuration, the AD8138 output was offset to 1.5 V and R1 was
adjusted to provide the appropriate operating current. The
buffer amplifier was then used; still any capacitance added at
the VLOG Pin during measurement would form a filter with the
on-chip 5 k
resistor.
The configuration illustrated in Figure 21 measures the device
noise. Batteries provide both the supply and the input signal to
remove the supplies as a possible noise source and to reduce
ground loop effects. The AD8304 Evaluation Board and the
current setting resistors are mounted in closed aluminum enclo-
sures to provide additional shielding to external noise sources.
SOURCE
TRIGGER
CHANNEL
1
HP 89410A
CHANNEL
2
VNEG
PWDN
VSUM
INPT
VSUM
VPDB
VREF
ACOM
BFNG
VPS1
VOUT
VPS2
BFIN
VLOG
1
2
3
4
5
6
7
14
13
12
11
10
9
8
R1
750
1nF
ALKALINE
D CELL
ALKALINE
D CELL
AD8304
Figure 21. Configuration for Noise Spectral
Density Measurement
Evaluation Board
An evaluation board is available for the AD8304, the schematic
for which is shown in Figure 22, and the two board sides are
shown in Figure 23 and Figure 24. It can be configured for a wide
variety of experiments. The board is factory set for Photocon-
ductive Mode with a buffer gain of unity, providing a slope of
10 mV/dB and an intercept of 100 pA. By substituting resistor and
capacitor values, all of the application circuits presented in this
data sheet can be evaluated. Table V describes the various configu-
ration options.
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