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參數(shù)資料
| 型號： | AD8304ARU-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGARITHMIC CONV 14-TSSOP T/R |
| 設計資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標準包裝： | 1,000 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. A
–16–
AD8304
6
3
4
PDB
BIAS
VREF
10
2
12
VPDB
VSUM
INPT
VSUM
5
1
VNEG
~10k
ACOM
14
VPS2
PWDN
VPS1
VREF
7
VLOG
8
BFIN
9
BFNG
TEMPERATURE
COMPENSATION
5k
11
VOUT
0.5V
IPD
NC
R1
750
C1
1nF
13
VP
NC = NO CONNECT
RB
VOUT
VN (–0.5V TO –3V)
10nF
VOFS
AD8304
Figure 15. Using the Buffer to Invert the Polarity
of the Slope
When the gain is set to 13 (RB = 5 k
) the 2 V VREF can be tied
directly to BFIN, in which case the starting point for the output
response is at 4 V. However, since the slope in this case is only
–0.2 V/decade, the full current range will only take the output
down by 1.6 V. Clearly, a higher slope (or gain) is desirable, in
which case VOFS should be set to a smaller voltage to avoid railing
the output at low currents. If VOFS = 1.2 V and G = 33, VOUT
now starts at 4.8 V and falls through this same voltage toward
ground with a slope of –0.6 V per decade, spanning the full
range of IPD.
Programmable Level Comparator with Hysteresis
The buffer amplifier and reference voltage permit a calibrated
level detector to be realized. Figure 16 shows the use of a 10-bit
MDAC to control the setpoint to within 0.1 dB of an exact value
over the 100 dB range of 1 nA
≤ I
PD
≤ 100 A when the full-
scale output of the MDAC is equal to that of its reference. The
2 V VREF also sets the minimum value of VSPT to 0.2 V, correspond-
ing to an input of 1 nA. Since 100 dB at the VLOG interface
corresponds to a 1 V span, the resistor network is calculated to
provide a maximum VSPT of 1.2 V while adding the required
10% of VREF.
In this example, the hysteresis range is arranged to be 0.1 dB,
(1 mV at VLOG) when using a 5 V supply. This will usually be
adequate to prevent noise that causes the comparator output to
thrash. That risk can be reduced further by using a low-pass filtering
capacitor at VLOG (shown dotted) to decrease the noise bandwidth.
6
3
4
PDB
BIAS
VREF
10
2
12
VPDB
VSUM
INPT
VSUM
5
1
VNEG
~10k
ACOM
14
VPS2
PWDN
VPS1
VREF
7
VLOG
8
BFIN
9
BFNG
TEMPERATURE
COMPENSATION
5k
11
VOUT
0.5V
IPD
NC
750
1nF
13
VP
NC = NO CONNECT
50M
VOUT
10nF
VSPT
VREF
VOUT
MDAC
49.9k
100k
RH
AD8304
Figure 16. Calibrated Level Comparator
6
3
4
PDB
BIAS
VREF
10
2
12
VPDB
VSUM
INPT
VSUM
5
1
VNEG
~10k
ACOM
14
VPS2
PWDN
VPS1
VREF
7
VLOG
8
BFIN
9
BFNG
TEMPERATURE
COMPENSATION
5k
11
VOUT
0.5V
ISRC
25k
NC
13
VP
NC = NO CONNECT
C2
1nF
VN (–0.5V TO –5V)
1k
VREF
VOUT
MDAC
C1
10nF
100k
AD8304
Figure 17. Multidecade Current Source
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參數(shù)描述 |
|---|---|
| AD8304ARUZ | 功能描述:IC LOGARITHM CONV 160DB 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應商設備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8304ARUZ | 制造商:Analog Devices 功能描述:Logarithmic Amplifier IC |
| AD8304ARUZ-RL7 | 功能描述:IC LOGARITHM CONV 160DB 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應商設備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8304-EVAL | 制造商:Analog Devices 功能描述:LTSSOP 160DB-RANGE LOGARITHMIC CONVERTER - Bulk |
| AD8304-EVALZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 160 DB Range Logarithmic Converter 制造商:Analog Devices 功能描述:EVAL KIT FOR 160 DB RANGE (100 PA -10 MA) LOGARITHMIC CNVRTR - Bulk 制造商:Analog Devices 功能描述:EVAL LOGARITHMIC DECTECTOR AD8304 |
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