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參數(shù)資料
| 型號： | AD8368ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC AMP VGA 24LFCSP |
| 設(shè)計資源： | Extending the Dynamic Range of ADL5513 Logarithmic Detector Using AD8368 (CN0072) |
| 標準包裝： | 1 |
| 系列： | X-AMP® |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 800MHz |
| 電流 - 電源： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 其它名稱： | AD8368ACPZ-REEL7DKR |
AD8368
Rev. B | Page 12 of 20
CIRCUIT DESCRIPTION
The AD8368 is a single-ended VGA with a bandwidth of 800 MHz
and a gain control span of 34 dB ranging from 12 dB to +22 dB.
It incorporates an uncommitted square law detector that can be
used to form a tight AGC loop around the VGA. Using the
Analog Devices patented X-AMP architecture, the AD8368
achieves accurate linear-in-dB gain control with excellent linearity
(OIP3) and noise figure (NF). The part also features 50 Ω input
and output impedances for ease of use.
The main signal path, shown in Figure 30, consists of a variable
input attenuator followed by a fixed-gain amplifier and output
buffer. This architecture allows for a constant OIP3 and output
noise floor as a function of gain setting. As a result, NF and IIP3
increase 1 dB for every 1 dB decrease in gain, resulting in a part
with constant dynamic range over gain setting.
05
90
7-
0
33
ATTENUATOR LADDER
DECL
50
0dB –2dB –4dB
–36dB
VOUT
INPT
GAIN
MODE
GAIN INTERPOLATOR
gm STAGES
FIXED-GAIN
AMPLIFIER
OUTPUT
BUFFER
Figure 30. Simplified Block Diagram
INPUT ATTENUATOR AND INTERPOLATOR
The input attenuator is built from an 18-section resistor ladder,
providing 2 dB of attenuation at each successive tap point. The
resistor ladder acts as a linear input attenuator, in addition to
providing an accurate 50 Ω input impedance. The variable
transconductance (gm) stages are used to select the attenuated
signal from the appropriate tap point along the ladder and feed
this signal to the fixed-gain amplifier. To realize a continuous gain
control function from discrete tap points, the gain interpolator
creates a weighted sum of signals appearing on adjacent tap
points by carefully controlling the variable gm stages.
FIXED-GAIN STAGE AND OUTPUT BUFFER
The weighted sum of the different tap points is fed into the
fixed-gain stage that drives the output buffer. Because the
resistive input attenuator is linear and contributes minimal
noise as a passive termination, the dynamic range as a function
of gain is determined primarily by the noise and the distortion
of the fixed-gain amplifier. This architecture explains the constant
OIP3 and constant output noise floor with gain setting and the
corresponding dB-for-dB increase in IIP3 and NF with decreasing
gain. The output buffer has 6 dB of gain and provides a broadband
50 Ω single-ended output impedance.
OUTPUT OFFSET CORRECTION
The dc level at the input, INPT, is driven by an internal reference to
VS/2. The reference is made available at the DECL pin for external
decoupling with CDECL. The dc level at the output, OUTP, is
regulated to the same midsupply reference by an offset correction
loop independent of gain setting, temperature, and process. The
low-pass response of this loop creates a high-pass corner frequency
in the signal path transfer function, which can be set by choosing
CDECL and CHPFL.
05
90
7-
0
34
VOUT
gm
FIXED-GAIN
AMPLIFIER
FROM
INTERPOLATOR
gm STAGES
OUTPUT
BUFFER
×1
VMID
DECL
CDECL
HPFL
CHPFL
Figure 31. Output Centering Control Loop
The input and output coupling capacitors should be selected to
provide low impedances at the frequencies of interest relative to
50 Ω so as not to affect the high-pass corner. In this case, the
high-pass corner frequency can be set by either CHPFL or CDECL,
which form independent poles in the feedback path of the offset
correction loop. The high-pass corner is determined by the highest
of these poles, which are given by
)
005
.
0
(
8
.
0
)
kHz
(
,
HPFL
HP
C
f
+
=
)
005
.
0
(
5700
)
kHz
(
,
DECL
HP
C
f
+
=
where CHPFL and CDECL are in nF.
When using this method to set the high-pass frequency, the
other capacitor should be sized such that its pole is at least 30×
lower in frequency. In addition, note that CDECL represents the
total decoupling capacitance at the DECL pins.
INPUT AND OUTPUT IMPEDANCES
The AD8368 offers single-ended broadband 50 Ω input and
output impedances. The excellent match to 50 Ω is maintained
from part to part, over frequency, and over gain setting. Both
the input and output pins must be externally ac-coupled to
prevent disruption of the internal dc levels. Sufficiently large
coupling capacitors should be used so that their impedance is
negligible relative to the 50 Ω presented by the ladder at the
input and by the output buffer at the output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8368ACPZ-WP | 功能描述:IC AMP VGA 24LFCSP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:X-AMP® 標準包裝:2,500 系列:- 放大器類型:通用 電路數(shù):1 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.11 V/µs 增益帶寬積:350kHz -3db帶寬:- 電流 - 輸入偏壓:4nA 電壓 - 輸入偏移:20µV 電流 - 電源:260µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):2.7 V ~ 36 V，±1.35 V ~ 18 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SO 包裝:帶卷 (TR) |
| AD8368-EVALZ | 制造商:Analog Devices 功能描述:EVAL BD 800 MHZ, LINEAR-IN-DB VGA W/ AGC DETECTOR - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD KIT |
| AD8369 | 制造商:AD 制造商全稱:Analog Devices 功能描述:45 dB Digitally Controlled VGA LF to 600 MHz |
| AD8369ARM | 制造商:Analog Devices 功能描述:500 MHZ DIGITAL VGA - Bulk |
| AD8369ARU | 制造商:Analog Devices 功能描述:SP Amp Variable Gain Amp Single 5.5V 16-Pin TSSOP Tube 制造商:Rochester Electronics LLC 功能描述:TSSOP IF DIGITAL CONTROL VGA - Bulk 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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