參數(shù)資料
型號: AD8368ACPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 7/20頁
文件大?。?/td> 0K
描述: IC AMP VGA 24LFCSP
設計資源: Extending the Dynamic Range of ADL5513 Logarithmic Detector Using AD8368 (CN0072)
標準包裝: 1
系列: X-AMP®
放大器類型: 可變增益
電路數(shù): 1
-3db帶寬: 800MHz
電流 - 電源: 60mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應商設備封裝: 24-LFCSP-VQ(4x4)
包裝: 標準包裝
產品目錄頁面: 775 (CN2011-ZH PDF)
其它名稱: AD8368ACPZ-REEL7DKR
AD8368
Rev. B | Page 15 of 20
The output setpoint can be increased using an external resistive
divider network between OUTP and DETI, referenced to DECL
as depicted in Figure 34. In this configuration, the rms output
voltage is forced to (1 + R1/R2) 63 mV rms by the AGC loop.
For a 0 dBm (224 mV rms referenced to 50 Ω) output setpoint,
this ratio is 3.5. After correcting for the input impedance of
DETI, the choice of R1 = 226 Ω and R2 = 100 Ω yields a setpoint of
roughly 0 dBm. This very accurate leveling function is shown in
Figure 35, where the rms output is held to within 0.2 dB of the
0 dBm setpoint for >30 dB range of input levels.
10
–30
–25
–20
–15
–10
–5
0
5
–40
–30
–20
–10
0
10
20
PO
W
E
R
O
U
T
(
d
B
m
)
POWER IN (dBm)
05
90
7-
0
38
Figure 35. Output Power vs. Input Power in AGC Mode at 140 MHz
Note that to achieve the accurate level of AGC output power,
the DECL capacitor must be adjusted for the corresponding RF
frequency. The DECL capacitor value varies depending on board
parasitics. Table 5 shows the DECL capacitor value based on the
evaluation board parasitics.
Table 5. DECL Capacitor Value
IF Frequency (MHz)
C4 (pF)
C20 (pF)
70
1000
2200
140
270
560
240
68
150
380
33
68
480
15
39
A valuable feature of using a square law detector in AGC mode
is that the RSSI voltage is a true reflection of signal power and
can be converted to an absolute power measurement for any
given source impedance. The RSSI in units of dBm referenced
to 50 Ω and based on the voltage available on the DETO pin is
given by
RSSI
= 11 + 20 log10(1 + R1/R2) + 38 × VDETO 24.8
Figure 36 shows a plot of the RSSI voltage at DETO as input
power is swept.
3.0
0
0.5
1.0
1.5
2.0
2.5
–40
–30
–20
–10
0
10
20
RS
S
I(
V
)
POWER IN (dBm)
05
90
7-
0
39
Figure 36. Monitoring the GAIN/DETO RSSI Voltage vs. Input Power
In some cases, it can be found that, if driven into AGC overload,
the AD8368 requires unusually long times to recover; that is, the
voltage at DETO remains at an abnormally high value, and the
gain is at its lowest value. To avoid this situation, it is recommended
that a clamp be placed on the DETO pin, as shown in Figure 37.
05
90
7-
0
42
IC
OM
GA
IN
ENBL
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSI
IC
OM
DE
T
O
IC
OM
HP
F
L
DE
CL
DE
CL
DE
CL
DE
T
I
V
PSI
OC
OM
AD8368
CAGC
0.1F
VAGC
Q1
2N2907
RB
0.5V
RA
+VS
Figure 37. External Clamp to Prevent AGC Overload
The resistive divider network, RA and RB, should be designed
such that the base of Q1 is driven to 0.5 V.
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