The choice of CDETO is a compromise of averaging time con" />
參數(shù)資料
型號(hào): AD8368ACPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/20頁(yè)
文件大?。?/td> 0K
描述: IC AMP VGA 24LFCSP
設(shè)計(jì)資源: Extending the Dynamic Range of ADL5513 Logarithmic Detector Using AD8368 (CN0072)
標(biāo)準(zhǔn)包裝: 1
系列: X-AMP®
放大器類型: 可變?cè)鲆?br>
電路數(shù): 1
-3db帶寬: 800MHz
電流 - 電源: 60mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 775 (CN2011-ZH PDF)
其它名稱: AD8368ACPZ-REEL7DKR
AD8368
Rev. B | Page 16 of 20
The choice of CDETO is a compromise of averaging time constant,
response time, and carrier leakage. If CDETO is selected to be too
small to speed up the response time, the AGC loop could start
tracking and leveling any amplitude envelope and corrupt the
constellation. Figure 38 illustrates a 16 QAM, 100 ksymbols per
second constellation with a degraded error vector magnitude
(EVM) of 5%. By increasing CDETO to 0.01 μF, the EVM is
improved to 1.1%.
STABILITY AND LAYOUT CONSIDERATIONS
In some applications, the printed circuit board (PCB) parasitic, in
combination with the source impedance presented by the driving
stage, can present some troublesome impedance at high frequency
and can potentially unstablize the amplifier under certain extreme
conditions, such as high gain and high temperature. To avoid such
scenarios, it is recommended to include a simple parallel RL
snubbing network directly at the input terminal of the AD8368.
Figure 40 depicts an example of this network. The RL network
formed by R3 and L1 is used to minimize the negative impact
due to reflective source conditions at high RF frequencies and
ensures the amplifier operates unconditionally stable and
maintains the typical device performance.
REF –4.9dBm
CF 100MHz
SR 10kHz
CONST DIAG
MEAS SIGNAL
16 QAM
1U
–1U
–1.31289U
262.578mU/
1.31289U
05
90
7-
0
40
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
ground of the chip. Solder the paddle to the low impedance ground
plane on the PCB to ensure specified electrical performance and to
provide thermal relief. It is also recommended that the ground
planes on all layers under the paddle be stitched together with
vias to reduce thermal impedance.
Figure 38. Degraded Error Vector Magnitude Performance for 16 QAM at
100 ksymbols per second (CDETO Too Small)
Figure 39 illustrates the measured EVM performance for a 16 QAM
modulation at 10 Msymbols per second using CDETO = 1 nF.
10
0
1
2
3
4
5
6
7
8
9
–40
–30
–20
–10
0
10
20
EV
M
(
%
)
POWER IN (dBm)
05
90
7-
0
41
Figure 39. Error Vector Magnitude Performance for
16 QAM 10 Msymbols per second
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