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參數(shù)資料
| 型號： | AD8600APZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC MULT 16CH 8BIT 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 175mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 16 電壓，單極；16 電壓，雙極 |
| 采樣率（每秒）： | 1M |
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
1
Resolution
N
8
Bits
Total Unadjusted Error
TUE
All Other DACs Loaded with Data = 55H
–1
±3/4
+1
LSB
Relative Accuracy
INL
–1
±1/2
+1
LSB
Differential Nonlinearity
DNL
Guaranteed Monotonic
–1
±1/4
+1
LSB
Full-Scale Voltage
VFS
Data = FFH, VREF = +3.5 V
3.473
3.486
3.500
V
Full-Scale Voltage Error
VFSE
Data = FFH, VREF = +3.5 V
–1
+1
LSB
Full-Scale Tempco
TCVFS
Data = FFH, VREF = +3.5 V
±20
ppm/
°C
Zero Scale Error
VZSE
Data = 00H, RS = “0,” TA = +25°C–2
±1+2
mV
Zero Scale Error
VZSE
Data = 00H, All Other DACs Data = 00H
–1
+1
LSB
Zero Scale Error
VZSE
Data = 00H, All Other DACs Data = 55H
±1/2
LSB
Zero Scale Tempco
TCVZS
Data = 00H, VCC = +5 V, VEE = –5 V
±10
V/°C
Reference Input Resistance
RREF
Data = ABH
1.2
2
k
Reference Input Capacitance
2
CREF
Data = ABH
240
pF
ANALOG OUTPUT
Output Voltage Range
OVR1
VREF = +3.5 V
0.000
3.500
V
Output Voltage Range
2
OVR2
VCC = VDD2 = +7 V, VEE = –0.7 V, VREF = 5 V
0.000
5.000
V
Output Current
IOUT
Data = 80H
±2mA
Capacitive Load
2
CL
No Oscillation
50
pF
LOGIC INPUTS
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Logic Input Current
IIL
10
A
Logic Input Capacitance
2
CIL
10
pF
LOGIC OUTPUTS
Logic Out High Voltage
VOH
IOH = –0.4 mA
3.5
V
Logic Out Low Voltage
VOL
IOL = 1.6 mA
0.4
V
AC CHARACTERISTICS
2
Reference In Bandwidth
BW
–3 dB Frequency, VREF = 2.5 VDC + 0.1 VAC
500
kHz
Slew Rate
SR
For
V
REF or FS Code Change
4
7
V/
s
Voltage Noise Density
eN
f = 1 kHz, VREF = 0 V
46
nV/
√Hz
Digital Feedthrough
FT
Digital Inputs to DAC Outputs
10
nVs
Voltage Output Settling Time
3
tS1
±1 LSB of Final Value, FS Data Change
1
2
s
Voltage Output Settling Time
3
tS2
±1 LSB of Final Value, V
REF = 1 V, Data = FFH
12
s
POWER SUPPLIES
Positive Supply Current
ICC
VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load
22
35
mA
Negative Supply Current
IEE
VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load
22
35
mA
Logic Supply Currents
IDD1&2
VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load
0.1
mA
Power Dissipation
4
PDISS
VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load
225
350
mW
Power Supply Sensitivity
PSS
V
CC & VEE = ± 5%
0.007
%/%
Logic Power Supply Range
VDDR
4.75
5.25
V
Pos Power Supply Range
2
VCCR
VDD
7.0
V
Neg Power Supply Range
2
VEER
–5.25
0.0
V
NOTES
1When V
REF = +3.500 V, 1 LSB = 13.67 mV.
2Guaranteed by design not subject to production test.
3Settling time test is performed using R
L = 50 k and CL = 35 pF.
4Power Dissipation is calculated using 5 V
× (I
DD + |ISS| + IDD1 + IDD2).
Specifications subject to change without notice.
DUAL SUPPLY (@ V
DD1 = VDD2 = VCC = +5 V
± 5%, V
EE = –5 V
± 5%, V
REF = +3.500 V, – 40
°C ≤ T
A
≤ +85°C, unless otherwise noted)
AD8600
REV. 0
–3–
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