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參數(shù)資料
| 型號： | AD8600APZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC MULT 16CH 8BIT 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 500 |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 175mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 16 電壓，單極；16 電壓，雙極 |
| 采樣率（每秒）： | 1M |
REV. 0
–6–
AD8600
TRANSFER EQUATIONS
Output Voltage
O
i = D ×
V
REF
256
where i is the DAC channel number and D is the decimal value
of the DAC register data.
Table I. Truth Table
EN
R/W
CS LD
RS
Operation
Write to DAC Register
–
X
H
L
H
Update DAC Register
L
X
H
–
H
Update DAC Register
+
X
H
L
H
Latches DAC Register
L
X
H
+
H
Latches DAC Register
L
H
DAC Register Transparent
Write to Input Register
L
H
Load Data to Input Register at
Decoded Address
+
L
H
Latches Data in Input Register at
Decoded Address
L
+
H
Latches Data in Input Register at
Decoded Address
Readback Input Registers
X
H
L
H
Input Register Readback (Data
Access)
X
H
+
H
Hi-Z Readback Disconnects from
Bus
X
H
X
Hi-Z on Data Bus
Reset
X
L
Clear All Registers to Zero,
VOUT = 0 V
X
H
+
Latches All Registers to Zero
LX
LH
+
CS
= Low; Input Register Ready
for R/W, DAC Register Latched
to Zero
NOTES
1+ symbol means positive edge of control input line.
2– symbol means negative edge of control input line.
Decoded DAC Register
O
i = A
where A is the decimal value of the decoded address bits A3,
A2, A1, A0 (LSB).
Address, CS, R/W and data inputs should be stable prior to acti-
vation of the active low EN input. Input registers are transpar-
ent when EN is low. When EN returns high, data is latched into
the decoded input register. When the load strobe LD and EN
pins are active low, all input register data is transferred to the
DAC registers. The DAC registers are transparent while they
are enabled.
Table II. Address Decode Table
A3
A2
A1
A0
Addr
DAC
(MSB)
(LSB)
Code
Updated
(Binary)
(Hex)
000
0
O0
000
1
O1
001
0
2
O2
001
1
3
O3
010
0
4
O4
010
1
5
O5
011
0
6
O6
011
1
7
O7
100
0
8
O8
100
1
9
O9
101
0
A
O10
101
1
B
O11
110
0
C
O12
110
1
D
O13
111
0
E
O14
111
1
F
O15
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