REV. A
–15–
AD872A
Figure 32 shows how a dc offset can be applied using the
AD568 12-bit, high speed digital-to-analog converter (DAC).
This circuit can be used for applications requiring offset adjust-
ments on every clock cycle. The AD568 connection scheme is
used to provide a –0.512 V to +0.512 V output range. The off-
set voltage must be stable on the rising edge of the AD872A
clock input.
1
2
V
INA
V
INB
AD872A
IBPO
IOUT
RL
ACOM
LCOM
REF COM
AD568
74
HC
574
74
HC
574
8
4
DIGITAL
OFFSET
WORD
V
IN
Figure 32. Offset Correction Using the AD568
UNDERSAMPLING USING THE AD872A AND AD9100
The AD872A’s on-chip THA optimizes transient response while
maintaining low noise performance. For super-Nyquist (under-
sampling) applications it may be necessary to use an external
THA with fast track-mode slew rate and hold mode settling
time. An excellent choice for this application is the AD9100, an
ultrahigh speed track-and-hold amplifier.
In order to maximize the spurious free dynamic range of the
circuit in Figure 33 it is advantageous to present a small signal
to the input of the AD9100 and then amplify the output to the
AD872A’s full-scale input range. This can be accomplished with
a low distortion, wide bandwidth amplifier such as the AD9617.
The circuit uses a gain of 3.5 to optimize S/(N+D).
For small scale input signals (–20 dB, –40 dB), the AD872A
performs better without the track-and-hold because slew-
limiting effects are no longer dominant. To gain the advantages
of the added track-and-hold, it is important to give the AD872A
a full-scale input.
An alternative to the configuration presented above is to use the
AD9101 track-and-hold amplifier. The AD9101 provides a
built-in post amplifier with a gain of 4, providing excellent ac
characteristics in conjunction with a high level of integration.
As illustrated in Figure 33, it is necessary to skew the AD872A
sample clock and the AD9100 sample/hold control. Clock skew
(tS) is defined as the time starting at the AD9100’s transition
into hold mode and ending at the moment the AD872A samples.
The AD872A samples on the rising edge of the sample clock,
and the AD9100 samples on the falling edge of the sample/hold
control. The choice of tS is primarily determined by the settling
time of the AD9100. The droop rate of the AD9100 must also
be taken into consideration. Using these values, the ideal tS is
17 ns. When choosing clock sources, it is extremely important
that the front end track-and-hold sample/hold control is given a
very low jitter clock source. This is not as crucial for the
AD872A sample clock, because it is sampling a dc signal.
Figure 33. Undersampling Using the AD872A and AD9100
AD9100
2
3
8
10
17
13
12
11
6
15
1
5
7
14
16
20
4
19
18
AD872A
EB
CLOCK 1
+VS –VS
1
5
7Q
9
10
4
8
Q
R
T
510
–VS –VS
R
T
+V
S
10 F
–VS
127
7
2
3
4
5*
6
8*
0.1 F
3.3 F
–5V
442
0.1 F
3.3 F
+5V
CLOCK 2
* OPTIONAL, SEE
AD9617 DATASHEET
+VS = 5.0V
–VS = –5.2V
ALL CAPACITORS ARE 0.01 F
(LOW INDUCTANCE - DECOUPLING)
UNLESS OTHERWISE NOTED.
T = 200ns
CLOCK 2
CLOCK 1
t
S = 17ns
t
S
T = 200ns
+5V
0V
+1V
–1V
AD
96685
AD
9617
V
IN
AIN
IN
OBSOLETE