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| 型號： | AD9042ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 41MSPS 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 41M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 735mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
AD9042
Rev. B | Page 18 of 24
NOISE FLOOR AND SNR
Oversampling is the act of sampling at a rate that is greater than
twice the bandwidth of the signal desired. Oversampling has
nothing to do with the actual frequency of the sampled signal. It is
the bandwidth of the signal that is key. Band-pass or IF sampling
refers to sampling a frequency that is higher than Nyquist and
often provides additional benefits such as downconversion
using the ADC and track-and-hold as a mixer. Oversampling
leads to processing gains because the faster the signal is digitized,
the wider the distribution of noise. Because the integrated noise
must remain constant, the actual noise floor is lowered by 3 dB
each time the sample rate is doubled. The effective noise density
for an ADC may be calculated by the following equation:
FS
Hz
V
SNR
rms
NOISE
4
10
/
20
/
=
For a typical SNR of 68 dB and a sample rate of 40.96 MSPS, this is
equivalent to 31 nV/√Hz . This equation shows the relationship
between the SNR of the converter and the sample rate FS. This
equation can be used todetermine overall receiver noise.
The SNR for an ADC can be predicted. When normalized to
ADC codes, the following equation accurately predicts the SNR
based on three terms. These are jitter, average DNL error, and
thermal noise. Each of these terms contributes to the noise
within the converter.
()
+
ε
+
×
π
=
2
/
1
2
12
2
12
2
1
2
log
20
rms
NOISE
rms
J
ANALOG
V
t
F
SNR
where
FANALOG is analog input frequency.
t J rms is rms jitter of the encode (rms sum of encode source and
internal encode circuitry).
ε is average DNL of the ADC.
VNOISE rms is V rms thermal noise referred to the analog input of
the ADC.
PROCESSING GAIN
Processing gain is the improvement in SNR gained through
DSP processes. Most of this processing gain is accomplished
using the channelizer chips. These special-purpose DSP chips
not only provide channel selection and filtering but also provide
a data rate reduction. Few, if any, general-purpose DSPs can accept
and process data at 40.96 MSPS. The required rate reduction is
accomplished through a process called decimation. The term
decimation rate is used to indicate the ratio of input data rate to
output data rate. For example, if the input data rate is 40.96 MSPS
and the output data rate is 30 kSPS, then the decimation rate
is 1365.
Large processing gains may be achieved in the decimation
and filtering process. The purpose of the channelizer, beyond
tuning, is to provide the narrow-band filtering and selectivity
that traditionally has been provided by the ceramic or crystal
filters of a narrow-band receiver. This narrow-band filtering is
the source of the processing gain associated with a wideband
receiver and is simply the ratio of the pass-band to whole band
expressed in dBc. For example, if a 30 kHz AMPS signal is
digitized with an AD9042 sampling at 40.96 MSPS, the ratio is
0.030 MHz/20.48 MHz. Expressed in log form, the processing
gain is 10 × log (0.030 MHz/20.48 MHz) or 28.3 dB.
Additional filtering and noise reduction techniques can be
achieved through DSP techniques; many applications obtain
additional process gains through proprietary noise reduction
algorithms.
OVERCOMING STATIC NONLINEARITIES WITH
DITHER
Typically, high resolution data converters use multistage techniques
to achieve high bit resolution without large comparator arrays
that would be required if traditional flash ADC techniques were
used. The multistage converter typically provides better wafer
yields, meaning lower cost and much lower power. However,
because it is a multistage device, certain portions of the circuit
are used repetitively as the analog input sweeps from one end of
the converter range to the other. Although the worst DNL error
may be less than 1 LSB, the repetitive nature of the transfer
function can create havoc with low level dynamic signals. Spurious
signals for a full-scale input may be 88 dBc; however, at 29 dB
below full scale, these repetitive DNL errors can cause SFDR to
fall to 80 dBc as shown in Figure 13.
A common technique for randomizing and reducing the effects
of repetitive static linearity is through the use of dither. The
purpose of dither is to force the repetitive nature of static linearity
to appear as if it were random. Then, the average linearity over
the range of dither dominates the SFDR performance. In the
AD9042, the repetitive cycle is every 15.625 mV p-p.
To ensure adequate randomization, 5.3 mV rms is required; this
equates to a total dither power of 32.5 dBm. This randomizes
the DNL errors over the complete range of the residue converter.
Although lower levels of dither such as that from previous
analog stages reduces some of the linearity errors, the full effect
is gained only with this larger dither. Increasing dither even
more can be used to reduce some of the global INL errors.
However, signals much larger than the microvolts proposed in
this data sheet begin to reduce the usable dynamic range of the
converter.
Even with the 5.3 mV rms of noise suggested, SNR is limited to
36 dB if injected as broadband noise. To avoid this problem,
noise can be injected as an out-of-band signal. Typically, this may
be around dc but may just as well be at FS/2 or at some other
frequency not used by the receiver. The bandwidth of the noise
is several hundred kilohertz. By band-limiting and controlling
its location in frequency, large levels of dither can be introduced
into the receiver without seriously disrupting receiver
performance. The result can be a marked improvement in the
SFDR of the data converter.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9042BD | 制造商:Analog Devices 功能描述:- Bulk |
| AD9042CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042D | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042D/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042DPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
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