參數(shù)資料
型號(hào)： AD9117BCPZRL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/52頁(yè)
文件大小： 0K
描述： IC DAC DUAL 14BIT LO PWR 40LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142)
標(biāo)準(zhǔn)包裝： 750
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 232mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 4 電流，單極
采樣率（每秒）： 125M
AD9114/AD9115/AD9116/AD9117
Data Sheet
Rev. C | Page 40 of 52
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single
parallel bus (DB[n:0], where n is 7 for the AD9114, is 9 for the
AD9115, is 11 for the AD9116, and 13 for the AD9117)
accompanied by a qualifying clock (DCLKIO). The I and Q
data are provided to the chip in an interleaved double data rate
(DDR) format. The maximum guaranteed data rate is 250 MSPS
with a 125 MHz clock. The order of data pairing and the sampling
edge selection is user programmable using the IFIRST and
IRISING data control bits, resulting in four possible timing
diagrams. These timing diagrams are shown in Figure 89,
DCLKIO
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE
AD9116, AND 13 FOR THE AD9117.
DB[n:0]
Z
A
B
C
D
E
F
G
H
I DATA
Z
B
D
F
Q DATA
Y
A
C
E
07466-
051
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
DCLKIO
Z
A
B
C
D
E
F
G
H
I DATA
Y
A
C
E
Q DATA
X
Z
B
D
07466-
052
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE
AD9116, AND 13 FOR THE AD9117.
DB[n:0]
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
DCLKIO
Z
A
B
C
D
E
F
G
H
I DATA
Z
B
D
F
Q DATA
A
C
E
G
07466-
053
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE
AD9116, AND 13 FOR THE AD9117.
DB[n:0]
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
DCLKIO
Z
A
B
C
D
E
F
G
H
I DATA
Y
A
C
E
Q DATA
Z
B
D
F
07466-
054
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE
AD9116, AND 13 FOR THE AD9117.
DB[n:0]
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
Ideally, the rising and falling edges of the clock fall in the center
of the keep-in window formed by the setup and hold times, tS
and tH. Refer to Table 2 for setup and hold times. A detailed
timing diagram is shown in Figure 93.
DCLKIO
DB[n:0]
tS tH
07466-
055
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE
AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117.
Figure 93. Setup and Hold Times for All Input Modes
In addition to the different timing modes listed in Table 2, the
input data can also be presented to the device in either unsigned
binary or twos complement format. The format type is chosen
via the TWOS data control bit.
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