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| 型號： | AD9148-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/72頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9148 |
| 設(shè)計資源： | AD9148-EBZ Schematic AD9148-EBZ BOM AD9148-EBZ Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 4 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 設(shè)置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9148 |
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AD9148
Data Sheet
Rev. B | Page 46 of 72
The following procedure outlines the steps required to synchronize
multiple devices. The procedure assumes that the REFCLK/SYNC
signal is applied to all of the devices and the PLL of each device
is phase locked to it. Each individual device must follow this
procedure.
The procedure for synchronization when using the PLL follows:
1. Configure for data rate, periodic synchronization by writing
0xC0 to the sync control register (Register 0x10).
2. Read the sync status register (Register 0x12) and verify that
the sync locked bit (Bit 6) is set high indicating that the device
achieved back-end synchronization and that the sync lost
bit (Bit 7) is low. These levels indicate that the clocks are
running with a constant and known phase relative to the
sync signal.
3. Reset the FIFO by strobing the FRAME signal high for at
least the time interval needed to load complete data to the
four DACs. Resetting the FIFO ensures that the correct data is
being read from the FIFO. This completes the synchronization
procedure, and at this stage, all devices should be synchronized.
To maintain synchronization, the skew between REFCLK/SYNC
signals of the devices must be less than tSKEW nanoseconds. There
is also a setup and hold time to be observed between the DCI and
data of each device and the REFCLK/SYNC signal. When resetting
the FIFO, the FRAME signal must be held high for at least the
time interval needed to load complete data to the four DACs
(one DCI period for dual-port mode and two DCI periods for
single-port or byte mode). A timing diagram of the input signals is
shown in Figure 54.
The example in Figure 54 shows a REFCLK/SYNC frequency equal
to the data rate. Whereas this is the most common situation, it is not
strictly required for proper synchronization. Any REFCLK/SYNC
frequency that satisfies the following equations is acceptable:
fSYNC = fDACCLK/2N and fSYNC ≤ fDATA
where N = 1, 2, 3, or 4.
For example, a configuration with 4× interpolation and clock
frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, and
fDATA = 200 MHz, fSYNC = 100 MHz would be a viable solution.
REFCLK(1)
REFCLK(2)
DCI(2)
FRAME(2)
tSKEW
tSU_DCI
tH_DCI
08910-
053
Figure 54. Timing Diagram Required for Synchronizing Two Devices
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