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| 型號： | AD9148-M5375-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9149, ADL5375 |
| 設計資源： | AD9148-M5375-EBZ Schematic AD9148-M5375-EBZ BOM AD9148-M5375-EBZ Gerber Files |
| 標準包裝： | 1 |
| 系列： | * |
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AD9148
Data Sheet
Rev. B | Page 48 of 72
Generally, for values of N equal to or greater than 3, the FIFO
rate synchronization mode is chosen.
FIFO Rate Mode Synchronization
The following procedure outlines the steps required to synchronize
multiple devices in FIFO rate mode. The procedure assumes
that the CLK and REFCLK/SYNC signals are applied to all of the
devices. Each individual device must follow the procedure.
The procedure for FIFO rate synchronization when directly
sourcing the DAC sampling clock follows:
1. Configure for FIFO rate, periodic synchronization by writing
0x80 to the sync control register (Register 0x10). Additional
synchronization options are available and are described in
the Additional Synchronization Features section.
2. Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
3. Reset the FIFO by strobing the FRAME signal high for at
least the time interval needed to load complete data to the
four DACs. Resetting the FIFO ensures that the correct
data is being read from the FIFO of each of the devices
simultaneously. This completes the synchronization
procedure, and at this stage, all devices should be
synchronized.
To ensure that each of the DACs is updated with the correct
data on the same DACCLK edge, two timing relationships must
be met on each DAC. DCI (and data) must meet the setup and
hold times with respect to the rising edge of CLK, and REFCLK/
SYNC must also meet the setup and hold time with respect to
the rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dual-
port mode, and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within tSKEW + tOUTDLY nanoseconds of each other. A
timing diagram that illustrates the timing requirements of the
input signals is shown in Figure 57.
CLK(1)
CLK(2)
SYNC(2)
FRAME(2)
DCI(2)
tSKEW
tH_SYNC
tSU_SYNC
08910-
056
Figure 57. Synchronization Signal Timing Requirements in FIFO Rate Mode,
2× Interpolation
Figure 57 shows the synchronization signal timing with 2×
interpolation, so that fDCI = × fCLK. The REFCLK/SYNC input
is shown equal to the FIFO rate. The maximum frequency at which
the device can be resynchronized in FIFO rate mode can be
expressed as
N
DATA
SYNC
f
2
8×
=
for any positive integer, N.
ADDITIONAL SYNCHRONIZATION FEATURES
The synchronization logic incorporates additional features that
provide means for querying the status of the synchronization
and for improving the robustness of the synchronization. For
more information on these features, see the Sync Status Bits
section and the Timing Optimization section.
Sync Status Bits
When the sync locked bit (Bit 6, Register 0x12) is set, it indicates
that the synchronization logic has reached alignment. This is
determined when the clock generation state machine phase is
constant. This takes between (11 + Averaging) × 64 and (11 +
Averaging) × 128 DACCLK cycles. This bit may optionally trigger
an IRQ, as described in the Interrupt Request Operation section.
When the sync lost bit (Bit 7, Register 0x12) is set, it indicates that a
previously synchronized device has lost alignment. This bit is
latched and remains set until cleared by overwriting the register.
This bit may optionally trigger an IRQ as described in the
Timing Optimization
The REFCLK/SYNC signal is sampled by a version of the
DACCLK. If sampling errors are detected, the opposite sampling
edge can be selected to improve the sampling point. The sampling
edge can be selected by setting Bit 3, Register 0x10 (1 = rising
and 0 = falling).
The synchronization logic resynchronizes when a phase change
between the REFCLK/SYNC signal and the state of the clock
generation state machine exceeds a threshold. To mitigate the
effects of jitter and prevent erroneous resynchronizations, the
relative phase can be averaged. The amount of averaging is set
by the sync averaging bits (Bits[2:0], Register 0x10) and can be
set from 1 to 128. The higher the number of averages, the more
slowly the device recognizes and resynchronizes to a legitimate
phase correction. Generally, the averaging should be made as
large as possible while still meeting the allotted resynchronization
time interval.
Additional information on synchronization can be found in the
AN-1093 Application Note, Synchronization of Multiple AD9122
TxDAC+ Converters.
Table 15. Synchronization Setup and Hold Times
Parameter
Min
Max
Unit
tSKEW
tDACCLK/2
+tDACCLK/2
ps
tSU_SYNC
100
ps
tH_SYNC
+400
ps
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