TMIN to T
參數(shù)資料
型號(hào): AD9148-M5375-EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 45/72頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9149, ADL5375
設(shè)計(jì)資源: AD9148-M5375-EBZ Schematic
AD9148-M5375-EBZ BOM
AD9148-M5375-EBZ Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: *
Data Sheet
AD9148
Rev. B | Page 5 of 72
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ACCURACY
Differential Nonlinearity (DNL)
±2.1
LSB
Integral Nonlinearity (INL)
±3.7
LSB
MAIN DAC OUTPUTS
Offset Error
±0.001
% FSR
Gain Error (with Internal Reference)
±2
% FSR
Full-Scale Output Current1
8.66
20.2
31.66
mA
Output Compliance Range
1.0
+1.0
V
Output Resistance
10
Gain DAC Monotonicity
Guaranteed
Settling Time to Within ±0.5 LSB
20
ns
TEMPERATURE DRIFT
Main DAC Offset
0.04
ppm/°C
Main DAC Gain
100
ppm/°C
Reference Voltage
30
ppm/°C
REFERENCE
Internal Reference Voltage
1.2
V
Output Resistance
5
ANALOG SUPPLY VOLTAGES
AVDD33
3.13
3.3
3.47
V
CVDD18
1.71
1.8
1.89
V
DIGITAL SUPPLY VOLTAGES
IOVDD
1.71
1.8/3.3
3.47
V
DVDD18
1.71
1.8
1.89
V
POWER CONSUMPTION (NCO OFF, PLL DISABLED, AND SINC1 FILTER BYPASSED,
UNLESS OTHERWISE NOTED)
1 × Mode, fDAC = 300 MSPS, fINTERFACE = 600 MSPS
0.79
W
2 × Mode, fDAC = 500 MSPS, fINTERFACE = 500 MSPS
1.49
W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS
2.18
W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, NCO On
2.47
W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, PLL Enabled
2.26
W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, Sinc1 Filter Enabled
2.44
W
8 × Mode, fDAC = 800 MSPS, fINTERFACE = 200 MSPS
2.01
2.16
W
AVDD33
368
373
mW
CVDD18
261
280
mW
IOVDD
0.8
1.6
mW
DVDD18
1377
1504
mW
Power-Down Mode
1
12
mW
OPERATING RANGE
40
+25
+85
°C
1 Based on a 10 kΩ external resistor.
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