參數(shù)資料
型號: AD9219ABCPZRL7-65
廠商: Analog Devices Inc
文件頁數(shù): 12/56頁
文件大?。?/td> 0K
描述: IC ADC 10BIT SRL 65MSPS 64LFCSP
標準包裝: 750
位數(shù): 10
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 408mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;4 個差分,單極
AD9219
Data Sheet
Rev. E | Page 2 of 56
TABLE OF CONTENTS
REVISION HISTORY
12/11—Rev. D to Rev. E
Added Exposed Pad Notation to Figure 5................................... 11
Changes to Output Signals Section and Figure 71 ..................... 37
Change to Default Operation and Jumper Selection Settings
Section.............................................................................................. 38
Change to Figure 74 ....................................................................... 41
Changed LFCSP_WQ to LFCSP_VQ Throughout.................... 53
Added Endnote 2 in Ordering Guide .......................................... 53
5/10—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
4/10—Rev. B to Rev. C
Changes to Table 16........................................................................ 33
Updated Outline Dimensions ....................................................... 52
7/07—Rev. A to Rev. B
Changes to Figure 2 and Figure 4................................................... 7
Changes to Table 17........................................................................ 50
5/07—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Logic Output (SDIO/ODM) Section..........................5
Added Endnote 3 to Table 3.............................................................5
Changes to Pipeline Latency ............................................................6
Changes to Figure 2 to Figure 4.......................................................7
Changes to Figure 10...................................................................... 12
Changes to Figure 15, Figure 23 to Figure 26 Captions ............ 14
Changes to Figure 16, Figure 37, Figure 39, and Figure 40....... 14
Added Figure 46 and Figure 47 .................................................... 20
Change to Figure 50 ....................................................................... 21
Changes to Figure 51...................................................................... 21
Changes to Clock Duty Cycle Considerations Section ............. 22
Changes to Power Dissipation and
Power-Down Mode Section .......................................................... 23
Changes to Figure 58...................................................................... 23
Changes to Figure 61 to Figure 63 Captions............................... 25
Change to Table 8 ........................................................................... 25
Changes to Digital Outputs and Timing Section ....................... 26
Changes to Table 9 Endnote.......................................................... 26
Added Table 10 ............................................................................... 27
Deleted Figure 62 and Figure 63 .................................................. 27
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