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參數(shù)資料
| 型號： | AD9219ABCPZRL7-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SRL 65MSPS 64LFCSP |
| 標準包裝： | 750 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 65M |
| 數(shù)據接口： | 串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 功率耗散（最大）： | 408mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極 |
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AD9219
Data Sheet
Rev. E | Page 36 of 56
Power and Ground Recommendations
When connecting power to the AD9219, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts, with minimal
trace lengths.
A single PC board ground plane should be sufficient when
using the AD9219. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9219. An
exposed continuous copper plane on the PCB should mate to
the AD9219 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 70 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP), at www.analog.com.
SILKSCREEN PARTITION
PIN 1 INDICATOR
05
72
6-
01
3
Figure 70. Typical PCB Layout
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9219BCPZ-40 | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 40Msps 10-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 10BIT ADC QUAD 40MSPS LFCSP48 |
| AD9219BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 10-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 10BIT ADC QUAD 65MSPS LFCSP48 |
| AD9219BCPZRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219BCPZRL-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9220 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
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