參數(shù)資料
型號： AD9230BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 15/32頁
文件大小： 0K
描述： IC ADC 12BIT 170MSPS 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 371mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
AD9230
Rev. 0 | Page 22 of 32
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and CLK
pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 55 shows one preferred method for clocking the AD9230.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9230 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
06
00
2
-06
0
0.1F
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9230
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
Figure 55. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
06
002
-06
1
100
0.1F
240
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
501
CLK
150 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9230
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
Figure 56. Differential PECL Sample Clock
06
00
2
-07
0
CLOCK
INPUT
CLOCK
INPUT
100
0.1F
501
LVDS DRIVER
501
CLK
150 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9230
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 57. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 58). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
06
002
-07
1
0.1F
39k
CMOS DRIVER
501
OPTIONAL
100
0.1F
CLK
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9230
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
Figure 58. Single-Ended 1.8 V CMOS Sample Clock
0
600
2-
0
72
0.1F
CMOS DRIVER
CLK
150 RESISTOR IS OPTIONAL.
0.1F
CLK–
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
ADC
AD9230
CLOCK
INPUT
501
OPTIONAL
100
Figure 59. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9230 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9230. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the AD9230 Configuration
Using the SPI section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9230BCPZ-210 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 12B 210Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9230BCPZ-250 制造商:Analog Devices 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 56-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 250MSPS 12-BIT PARALLEL 56LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC ADC 12BIT 250MSPS LFCSP-56 制造商:Analog Devices Inc. 功能描述:Analog to Digital Converters - ADC 12-Bit 250 Msps ADC 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 250MSPS, LFCSP-56; Resolution (Bits):12bit; Sampling Rate:250MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:181mA; Digital IC Case Style:CSP; No. of Pins:56 ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:CONVERTER - ADC
AD9230BCPZRL7-170 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 12B 170Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9230XCPZ-170 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
AD9230XCPZ-210 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
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