參數(shù)資料
型號： AD9230BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 16/32頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 371mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
AD9230
Rev. 0 | Page 23 of 32
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log10[1/2 × π × fA × tJ]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 60).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9230.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
060
02
-0
65
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
SN
R
(
d
B
)
Figure 60. Ideal SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 42, the power dissipated by the AD9230 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
By asserting PDWN (Pin 29) high, the AD9230 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9230 into its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 20 MHz, the
AD9230 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9230 resumes normal
operation after allowing for the pipeline latency.
DIGITAL OUTPUTS
Digital Outputs and Timing
The AD9230 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more
information. The LVDS driver current is derived on-chip and
sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at the
receiver.
The AD9230 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length is no longer than 24 inches and that the
differential output traces are kept close together and at equal
lengths.
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 61. Figure 62 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
500
–500
–400
–300
–200
–100
0
100
200
300
400
–3
–2
–1
0
1
2
3
E
Y
E
DI
AG
RA
M
:V
O
L
T
AG
E
(
m
V
)
TIME (ns)
14
12
10
8
6
4
2
0
–40
–20
0
20
40
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(
H
it
s)
TIME (ps)
Figure 61. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
than 24 Inches on Standard FR-4, AD9230-250
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9230BCPZ-210 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 12B 210Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9230BCPZ-250 制造商:Analog Devices 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 56-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 250MSPS 12-BIT PARALLEL 56LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC ADC 12BIT 250MSPS LFCSP-56 制造商:Analog Devices Inc. 功能描述:Analog to Digital Converters - ADC 12-Bit 250 Msps ADC 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 250MSPS, LFCSP-56; Resolution (Bits):12bit; Sampling Rate:250MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:181mA; Digital IC Case Style:CSP; No. of Pins:56 ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:CONVERTER - ADC
AD9230BCPZRL7-170 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 12B 170Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9230XCPZ-170 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
AD9230XCPZ-210 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
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