參數(shù)資料
型號: AD9231BCPZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 14/36頁
文件大小: 0K
描述: IC ADC 12BIT 80MSPS 64LFCSP
標準包裝: 750
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 166.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
AD9231
Rev. A | Page 21 of 36
1V p-p
R
C
49.9
0.1F
10F
0.1F
AVDD
1k
ADC
AVDD
VIN+x
VIN–x
08
12
1-
00
9
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 43
shows a typical single-ended input configuration.
Figure 43. Single-Ended Input Configuration
ADC
R
0.1F
2V p-p
VCM
C
R
0.1F
S
0.1F
25
S
PA
P
VIN+x
VIN–x
08
12
1-
01
0
Figure 44. Differential Double Balun Input Configuration
AD8352
0
CD
RD
RG
0.1F
16
1
2
3
4
5
11
0.1F
10
14
0.1F
8, 13
VCC
200
ANALOG INPUT
R
C
ADC
VCM
VIN+x
VIN–x
08
12
1-
0
11
Figure 45. Differential Input Configuration Using the AD8352
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