參數(shù)資料
型號： AD9231BCPZRL7-80
廠商： Analog Devices Inc
文件頁數(shù)： 2/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 80MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 166.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
AD9231
Rev. A | Page 10 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D8B
D9B
DR
VD
D
D10B
(M
SB
)D1
1B
OR
B
DCO
B
DCO
A
NC
DR
VD
D
NC
(LSB
)D
0A
D1
A
D2
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AV
D
AV
D
VI
N
+
B
VI
N
–B
AV
D
AV
D
RB
IA
S
VC
M
SE
N
SE
VR
E
F
AV
D
AV
D
VI
N
–
A
VI
N
+
A
AV
D
AV
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
NC
(LSB) D0B
D1B
DRVDD
D2B
D3B
D4B
D5B
D6B
D7B
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO
ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D11A (MSB)
D10A
D9A
D8A
D7A
DRVDD
D6A
D5A
D4A
D3A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9231
TOP VIEW
(Not to Scale)
08
12
1-
0
05
Figure 5. Pin Configuration
Table 8. Pin Function Description
Pin No.
Mnemonic
Description
0
GND
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
1, 2
CLK+, CLK
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3
SYNC
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
4, 5, 6, 7, 25, 26, 27, 29
NC
Do Not Connect.
8 to 9, 11 to 18, 20, 21
D0B to D11B
Channel B Digital Outputs. D11B = MSB.
10, 19, 28, 37
DRVDD
Digital Output Driver Supply (1.8 V to 3.3 V).
22
ORB
Channel B Out-of-Range Digital Output.
23
DCOB
Channel B Data Clock Digital Output.
24
DCOA
Channel A Data Clock Digital Output.
30 to 36, 38 to 42
D0A to D11A
Channel A Digital Outputs. D11A = MSB.
43
ORA
Channel A Out-of-Range Digital Output.
44
SDIO/DCS
SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-
down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
45
SCLK/DFS
SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
46
CSB
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
47
OEB
Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high.
30 kΩ internal pull-down.
48
PDWN
Digital Input. 30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
相關(guān)PDF資料
PDF描述
VI-231-IW-F1 CONVERTER MOD DC/DC 12V 100W
VI-BNP-MW-F2 CONVERTER MOD DC/DC 13.8V 100W
MS3102E24-11P CONN RCPT 9POS BOX MNT W/PINS
VE-B3R-IV-F2 CONVERTER MOD DC/DC 7.5V 150W
PXA921/10/S CONN RCPT 10POS W/SKT LG CABLE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9233 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
AD9233-105EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
AD9233-105EBZ 制造商:Analog Devices 功能描述:
AD9233-125EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
AD9233-125EBZ 功能描述:BOARD EVALUATION FOR AD9233 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*