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參數(shù)資料
| 型號： | AD9233BCPZ-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 105MSPS 48-LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 配用： | AD9233-125EBZ-ND - BOARD EVALUATION FOR AD9233 |
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AD9233
Rev. A | Page 17 of 44
Single-Ended Input Configuration
Although not recommended, it is possible to operate the
AD9233 in a single-ended input configuration, as long as the
input voltage swing is within the AVDD supply. Single-ended
operation can provide adequate performance in cost-sensitive
applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode
swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 41
details a typical single-ended input configuration.
05
49
2-
0
42
1V p-p
R
C
49.9
0.1F
10F
0.1F
AVDD
1k
ADC
AD9233
AVDD
VIN+
VIN–
Figure 41. Single-Ended Input Configuration
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9233.
The input range is adjustable by varying the reference voltage
applied to the AD9233, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the following sections. The Reference
Decoupling section describes the best practices and requirements
for PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9233 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 42), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected external to the chip, as shown in Figure 43, the
switch again sets to the SENSE pin.
This puts the reference amplifier in a noninverting mode with
the VREF output defined as
+
×
=
1
R
2
R
1
5
.
0
VREF
If the SENSE pin is connected to the AVDD pin, the reference
amplifier is disabled, and an external reference voltage can be
applied to the VREF pin (see the External Reference Operation
section).
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VREF
SENSE
0.5V
AD9233
REFT
REFB
SELECT
LOGIC
0.1F
05
49
2-
0
43
VIN–
VIN+
ADC
CORE
–
Figure 42. Internal Reference Configuration
VREF
SENSE
0.5V
AD9233
VIN–
VIN+
REFT
REFB
SELECT
LOGIC
0.1F
R2
R1
05
49
2-
0
44
0.1F
ADC
CORE
–
Figure 43. Programmable Reference Configuration
If the internal reference of the AD9233 is used to drive multiple
converters to improve gain matching, the loading of the
reference by the other converters must be considered. Figure 44
depicts how the internal reference voltage is affected by loading.
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