參數(shù)資料
型號： AD9236BCPZRL7-80
廠商： Analog Devices Inc
文件頁數(shù)： 7/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 366mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個單端，單極；1 個差分，單極
Data Sheet
AD9236
Rev. C | Page 15 of 36
The SHA can be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
2
VREF
VCM MIN =
(
)
2
VREF
AVDD
VCM MAX
+
=
The minimum common-mode input level allows the AD9236 to
accommodate ground referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source can be applied to VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9236 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
can degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9236 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
AD9236
VIN+
VIN–
AGND
AVDD
1V p-p
49.9
523
1k
1k
0.1
F
33
33
20pF
499
499
499
AD8138
03066-0-013
Figure 28. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9236. This is especially true in IF
undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent
on the input frequency and source impedance and should be
reduced or removed. An example is shown in Figure 29.
03600-0-014
AD9236
VIN+
VIN–
AVDD
AGND
33
33
20pF
49.9
1k
1k
0.1
F
2V p-p
Figure 29. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing (see Figure 14). However, if
the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 30 details a typical
single-ended input configuration.
03600-A-015
AD9236
VIN+
VIN–
AVDD
AGND
2V p-p
33
33
20pF
49.9
1k
1k
0.33
F
10
F
0.1
F
1k
1k
+
Figure 30. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensitive
to clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance
characteristics. The AD9236 contains a clock
duty cycle stabilizer (DCS) that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows a wide range of clock input duty cycles
without affecting the performance of the AD9236. As shown in
Figure 22, noise and distortion performance is nearly flat for a
30% to 70% duty cycle with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
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