參數(shù)資料
型號(hào)： AD9236BCPZRL7-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/36頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 366mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9236
Data Sheet
Rev. C | Page 16 of 36
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fINPUT) due only to aperture jitter (tJ) can be calculated with the
following equation:
J
INPUT
t
f
SNR
2
1
log
20
10
In the equation, the rms aperture jitter represents the root-
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the
AD9236. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last step.
75
45
50
55
60
65
70
SNR
(
d
Bc
)
40
1
10
100
1000
INPUT FREQUENCY (MHz)
03066-0-043
0.2ps
MEASURED
SNR
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
Figure 31. SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 32, the power dissipated by the AD9236 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
N
f
C
V
I
CLK
LOAD
DRVDD
where N is the number of output bits, 12 in the case of the
AD9236. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
425
325
350
375
400
PO
WER
(
m
W)
140
120
100
80
60
40
20
0
CURRENT
(
m
A)
300
10
20
30
40
50
60
70
80
90
100
SAMPLE RATE (MSPS)
03066-0-044
ANALOG CURRENT
TOTAL POWER
DIGITAL CURRENT
Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 32
was taken with the same operating conditions as the Typical
Performance Characteristics, and with a 5 pF load on each
output driver.
By asserting the PDWN pin high, the AD9236 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During
standby, the output drivers are placed in a high impedance
state. Reasserting the PDWN pin low returns the AD9236
to its normal operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
DIGITAL OUTPUTS
The AD9236 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies, which can affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts can require external buffers or latches.
As detailed in Table 11, the data format can be selected for
either offset binary or twos complement.
相關(guān)PDF資料
PDF描述
AD9629BCPZRL7-80 IC ADC 12BIT 80MSPS 32LFCSP
MS27474T20B41PC CONN RCPT 41POS JAM NUT W/PINS
MS27484T12F4P CONN PLUG 4POS STRAIGHT W/PINS
MS3106F16-13P CONN PLUG 2POS STRAIGHT W/PINS
MS3102E22-12P CONN RCPT 5POS BOX MNT W/PINS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9236BRU-80 制造商:Analog Devices 功能描述:IC 12BIT ADC 3V 80MSPS SMD 9236
AD9236BRU-80EB 制造商:Analog Devices 功能描述:Evaluation Board For 12-Bit, 80 MSPS, 3 V A/D Converter
AD9236BRURL7-80 制造商:Analog Devices 功能描述:ADC Single Pipelined 80Msps 12-bit Parallel 28-Pin TSSOP T/R
AD9236BRUZ-80 功能描述:IC ADC 12BIT 80MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD9236BRUZRL7-80 功能描述:IC ADC 12BIT 80MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*