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參數(shù)資料
| 型號： | AD9236BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 80MSPS 32LFCSP |
| 標準包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 366mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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Data Sheet
AD9236
Rev. C | Page 17 of 36
TIMING
The AD9236 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9236. These transients can degrade the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9236 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance can degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9236. The input range can be adjusted by varying the
reference voltage applied to the AD9236 using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in Table 10
and described in the following sections.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
Internal Reference Connection
A comparator within the AD9236 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 10. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 33), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 34, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as follows:
R1
R2
VREF
1
5
.
0
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
03066-A-017
10
F
+
0.1
F
VREF
SENSE
0.5V
AD9236
VIN–
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 33. Internal Reference Configuration
03066-0-018
10
F
+
0.1
F
VREF
SENSE
R2
R1
0.5V
AD9236
VIN–
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 34. Programmable Reference Configuration
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD
N/A
2 × External Reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
R1
R2
1
5
.
0
2 × VREF
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
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| AD9236BRUZ-80 | 功能描述:IC ADC 12BIT 80MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9236BRUZRL7-80 | 功能描述:IC ADC 12BIT 80MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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