AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD9238BCP-65EBZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 45/48闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� BOARD EVAL WITH AD9238BCP-65
瑷�(sh猫)瑷堣硣婧愶細 AD9238 Eval Brd Gerber File
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
ADC 鐨勬暩(sh霉)閲忥細 2
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 65M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 骞惰伅(li谩n)
杓稿叆鑼冨湇锛� 2 Vpp
鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛夛細 640mW @ 65MSPS
宸ヤ綔婧害锛� -40°C ~ 85°C
宸茬敤 IC / 闆朵欢锛� AD9238-65
宸蹭緵鐗╁搧锛� 鏉�
鐩搁棞(gu膩n)鐢�(ch菐n)鍝侊細 AD9238BCPZ-20-ND - IC ADC 12BIT DUAL 20MSPS 64LFCSP
AD9238BCPZ-40-ND - IC ADC 12BIT DUAL 40MSPS 64LFCSP
AD9238BCPZ-65-ND - IC ADC 12BIT DUAL 65MSPS 64LFCSP
AD9238BSTZRL-40-ND - IC ADC 12BIT DUAL 40MSPS 64LQFP
AD9238BCPZRL-65-ND - IC ADC 12BIT DUAL 65MSPS 64LFCSP
AD9238BCPZRL-20-ND - IC ADC 12BIT DUAL 20MSPS 64LFCSP
AD9238BCPZRL-40-ND - IC ADC 12BIT DUAL 40MSPS 64LFCSP
AD9238BSTZ-40-ND - IC ADC 12BIT DUAL 40MSPS 64-LQFP
AD9238BSTRL-40-ND - IC ADC 12BIT DUAL 40MSPS 64-LQFP
AD9238BST-40-ND - IC ADC 12BIT DUAL 40MSPS 64-LQFP
AD9238
Rev. C | Page 6 of 48
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = 0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
Test
AD9238BST/BCP-20
AD9238BST/BCP-40
AD9238BST/BCP-65
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Full
IV
2.0
V
Low Level Input Voltage
Full
IV
0.8
V
High Level Input Current
Full
IV
10
+10
10
+10
10
+10
渭A
Low Level Input Current
Full
IV
10
+10
10
+10
10
+10
渭A
Input Capacitance
Full
IV
2
pF
LOGIC OUTPUTS1
High Level Output Voltage
Full
IV
DRVDD
0.05
DRVDD
0.05
DRVDD
0.05
V
Low Level Output Voltage
Full
IV
0.05
V
1 Output voltage levels measured with capacitive load only on each output.
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = 0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Test
AD9238BST/BCP-20
AD9238BST/BCP-40
AD9238BST/BCP-65
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
VI
20
40
65
MSPS
Minimum Conversion Rate
Full
V
1
MSPS
CLK Period
Full
V
50.0
25.0
15.4
ns
CLK Pulse-Width High1
Full
V
15.0
8.8
6.2
ns
CLK Pulse-Width Low1
Full
V
15.0
8.8
6.2
ns
DATA OUTPUT PARAMETER
Output Delay2 (tPD)
Full
VI
2
3.5
6
2
3.5
6
2
3.5
6
ns
Pipeline Delay (Latency)
Full
V
7
Cycles
Aperture Delay (tA)
Full
V
1.0
ns
Aperture Uncertainty (tJ)
Full
V
0.5
ps rms
Wake-Up Time3
Full
V
2.5
ms
OUT-OF-RANGE RECOVERY TIME
Full
V
2
Cycles
1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 渭F and 10 渭F capacitors on REFT and REFB.
N鈥�1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
ANALOG
INPUT
CLOCK
DATA
OUT
N鈥�9
N鈥�8
N鈥�7
N鈥�6
N鈥�5
N鈥�4
N鈥�3
N鈥�2
N鈥�1
N
MIN 2.0ns,
MAX 6.0ns
tPD =
02640-002
Figure 2. Timing Diagram
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
1210R-100K COIL .010UH PHENOLIC SMD
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD9238BCPZ-20 鍔熻兘鎻忚堪:IC ADC 12BIT DUAL 20MSPS 64LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:TSA1204 View All Specifications 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:20M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:155mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-TQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:48-TQFP锛�7x7锛� 鍖呰:Digi-Reel® 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:4 鍊嬪柈绔�锛屽柈妤�锛�2 鍊嬪樊鍒�锛屽柈妤� 鐢�(ch菐n)鍝佺洰閷勯爜闈�:1156 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:497-5435-6
AD9238BCPZ-20EB 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
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AD9238BCPZ-40 鍔熻兘鎻忚堪:IC ADC 12BIT DUAL 40MSPS 64LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 浣嶆暩(sh霉):14 閲囨ǎ鐜囷紙姣忕锛�:83k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛屽苟鑱�(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:95mW 闆诲闆绘簮:闆� ± 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:28-DIP锛�0.600"锛�15.24mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PDIP 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔紝闆欐サ
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