參數(shù)資料
型號： AD9251BCPZRL7-40
廠商： Analog Devices Inc
文件頁數(shù)： 20/36頁
文件大小： 0K
描述： IC ADC 14BIT 40MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 14
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 105.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
AD9251
Rev. A | Page 27 of 36
DIGITAL OUTPUTS
The AD9251 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number of
traces required.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 11. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
SCLK/DFS
SDIO/DCS
AGND
Offset binary (default)
DCS disabled
DRVDD
Twos complement
DCS enabled (default)
Digital Output Enable Function (OEB)
The AD9251 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB pin
or through the SPI interface. If the OEB pin is low, the output
data drivers and DCOs are enabled. If the OEB pin is high, the
output data drivers and DCOs are placed in a high impedance
state. This OEB function is not intended for rapid access to the
data bus. Note that OEB is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output disable (OEB) bit (Bit 4) in Register 0x14.
TIMING
The AD9251 provides latched data with a pipeline delay of
9 clock cycles. Data outputs are available one propagation delay
(tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9251. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9251 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9251 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of the DCO, unless the
DCO clock polarity has been changed via the SPI. See Figure 2
and Figure 3 for a graphical timing description.
Table 12. Output Data Format
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
OR
VIN+ VIN
< VREF 0.5 LSB
00 0000 0000 0000
10 0000 0000 0000
1
VIN+ VIN
= VREF
00 0000 0000 0000
10 0000 0000 0000
0
VIN+ VIN
= 0
10 0000 0000 0000
00 0000 0000 0000
0
VIN+ VIN
= +VREF 1.0 LSB
11 1111 1111 1111
01 1111 1111 1111
0
VIN+ VIN
> +VREF 0.5 LSB
11 1111 1111 1111
01 1111 1111 1111
1
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