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參數(shù)資料
| 型號： | AD9251BCPZRL7-40 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 40MSPS 64LFCSP |
| 標準包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 105.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9251
Rev. A | Page 30 of 36
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the programming device of the user and the serial port
of the AD9251. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is
bidirectional, functioning as an input during write phases and
as an output during readback.
The SPI interface is flexible enough to be controlled by
either FPGAs or microcontrollers. One method for SPI
configuration is described in detail in the AN-812 Appli-
cation Note, Microcontroller-Based Serial Port Interface
(SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9251 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
SDIO/DCS and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
AVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9251.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control pins.
When the device is powered up, it is assumed that the user
intends to use the pins as static control lines for the duty cycle
stabilizer, output data format, output enable, and power-down
feature control. In this mode, connect the CSB chip select to
AVDD, which disables the serial port interface.
Table 14. Mode Selection
Pin
External
Voltage
Configuration
SDIO/DCS
AVDD (default)
Duty cycle stabilizer enabled
AGND
Duty cycle stabilizer disabled
SCLK/DFS
AVDD
Twos complement enabled
AGND (default)
Offset binary enabled
OEB
AVDD
Outputs in high impedance
AGND (default)
Outputs enabled
PDWN
AVDD
Chip in power-down or standby
AGND (default)
Normal operation
SPI ACCESSIBLE FEATURES
Table 15 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9251 part-specific features are described in
detail in Table 16.
Table 15. Features Accessible Using the SPI
Feature
Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have known
data on output bits
Output Mode
Allows the user to set up outputs
Output Phase
Allows the user to set the output clock polarity
Output Delay
Allows the user to vary the DCO delay
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