AD9258
Rev. A | Page 10 of 44
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Limit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK+ setup time
0.30 ns typ
tHSYNC
SYNC to rising edge of CLK+ hold time
0.40 ns typ
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2 ns min
tDH
Hold time between the data and the rising edge of SCLK
2 ns min
tCLK
Period of the SCLK
40 ns min
tS
Setup time between CSB and SCLK
2 ns min
tH
Hold time between CSB and SCLK
2 ns min
tHIGH
SCLK pulse width high
10 ns min
tLOW
SCLK pulse width low
10 ns min
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
10 ns min
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
10 ns min
Timing Diagrams
tPD
tSKEW
tCH
tDCO
tCLK
N – 12
N – 13
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 11
N – 10
N – 9
N – 8
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
08
12
4-
00
2
Figure 2. CMOS Default Output Mode Data Output Timing
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 12
CH B
N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N – 9
CH B
N – 9
CH A
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
08
12
4-
0
57
Figure 3. CMOS Interleaved Output Mode Data Output Timing