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參數(shù)資料
| 型號(hào)： | AD9258BCPZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS DL 64LFCSP |
| 設(shè)計(jì)資源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 788mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
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AD9258
Rev. A | Page 37 of 44
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
channel index and transfer registers (Address 0x05 and
Address 0xFF); the ADC functions registers, including setup,
control, and test (Address 0x08 to Address 0x30); and the digital
feature control register (Address 0x100).
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x18, the VREF
select register, has a hexadecimal default value of 0xC0. This means
that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting
is the default reference selection setting. The default value uses a
2.0 V p-p reference. For more information on this function and
others, see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This application note details the functions con-
trolled by Register 0x00 to Register 0xFF. The remaining
register, Register 0x100 is documented in the Memory Map
Register Table section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD9258 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 through Address 0x18 and Address 0x30 are
shadowed. Writes to these addresses do not affect part operation
until a transfer command is issued by writing 0x01 to Address
0xFF, setting the transfer bit. This allows these registers to be
updated internally and simultaneously when the transfer bit is
set. The internal update takes place when the transfer bit is set,
and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated for
each channel. These registers and bits are designated in Table 17
as local. These local registers and bits can be accessed by setting
the appropriate Channel A or Channel B bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are set
during an SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 17 affect the entire
part or the channel features for which independent settings are not
allowed between channels. The settings in Register 0x05 do not
affect the global registers and bits.
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