參數(shù)資料
型號： AD9269BCPZRL7-20
廠商： Analog Devices Inc
文件頁數(shù)： 1/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS DL 64LFCSP
標準包裝： 750
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9269
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2010 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = 0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
ORA
D0A
D15A
DCOA
DRVDD
ORB
D15B
D0B
DCOB
SDIO
GND
AVDD
SCLK
SPI
QUADRATURE
ERROR
CORRECTION
PROGRAMMING DATA
MU
X
O
P
T
ION
PDWN DFS
CLK+ CLK–
MODE
CONTROLS
DCS
DUTY CYCLE
STABILIZER
SYNC
DIVIDE
1TO 6
OEB
CSB
REF
SELECT
ADC
CM
O
S
O
U
T
P
UT
BU
F
E
R
ADC
CM
O
S
O
UT
P
U
T
BUF
F
E
R
AD9269
0853
8-
001
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3.
An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4.
A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5.
The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
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