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參數(shù)資料
型號： AD9262BCPZ-10
廠商： Analog Devices Inc
文件頁數(shù)： 13/32頁
文件大小： 0K
描述： IC ADC 16BIT 10MHZ 64LFCSP
設(shè)計(jì)資源： Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
采樣率（每秒）： 160M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 762mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，單極
AD9262
Rev. A | Page 20 of 32
Table 11. Common Modulator Clock Multiplication Factors
CLK±
(MHz)
0x0A[5:0]
(PLLMULT)
fVCO
(MHz)
fMOD
(MHz)
BW
(MHz)
30.72
42
1290.24
645.12
10.08
39.3216
32
1258.29
629.15
9.83
52.00
25
1300.00
650.00
10.16
61.44
21
1290.24
645.12
10.08
76.80
17
1305.60
652.80
10.20
78.00
17
1326.00
663.00
10.36
78.6432
16
1258.29
629.15
9.83
89.60
15
1344.00
672.00
10.50
92.16
14
1290.24
645.12
10.08
122.88
10
1228.80
614.40
9.60
134.40
10
1344.00
672.00
10.50
153.60
8
1228.80
614.40
9.60
157.2864
8
1258.29
629.15
9.83
Jitter Considerations
The aperture jitter requirements for continuous time Σ-Δ conver-
ters may be more forgiving than Nyquist rate converters. The
continuous time Σ-Δ architecture is an oversampled system
and to accurately represent the analog input signal to the ADC,
a large number of output samples must be averaged together. As
a result, the jitter contribution from each sample is root sum
squared, resulting in a more subtle impact on noise perfor-
mance as compared to Nyquist converters where aperture
jitter has a direct impact on each sampled output.
In the block diagram of the continuous time Σ-Δ modulator
(see Figure 37), the two building blocks most susceptible to
jitter are the quantizer and the DAC. The error introduced
through the sampling process is reduced by the loop gain and
shaped in the same way as the quantization noise and, therefore,
its effect can be neglected. On the contrary, the jitter error
associated with the DAC directly adds to the input signal, thus
increasing the in-band noise power and degrading the modulator
performance. The SNR degradation due to jitter can be
represented by the following equation.
SNR = 20 log (2πfanalogtjitter_rms) dB
where fanalog is the analog input frequency and tjitter_rms is the jitter.
The SNR performance of the AD9262 remains constant within
the input bandwidth of the converter, from DC to 10 MHz.
Therefore, the minimal jitter specification is determined at the
highest input frequency. From the calculation, the aperture
jitter of the input clock must be no greater than 1 ps to achieve
optimal SNR performance.
POWER DISSIPATION AND STANDBY MODE
The AD9262 power consumption can be further reduced by
configuring the chip in channel power-down, standby, or sleep
mode. The low power modes turn off internal blocks of the chip,
including the reference. As a result, the wake-up time is depen-
dent on the amount of circuitry that is turned off. Fewer internal
circuits that are powered down result in proportionally shorter
wake-up time. The low power modes are shown in Table 12.
In the standby mode, all clock related activity and the output
channels are disabled. Only the references and CMOS outputs
remain powered up to ensure a short recovery and link integr-
ity. During sleep mode, all internal circuits are powered down,
putting the device into its lowest power mode, and the CMOS
outputs are disabled.
Each ADC channel can be independently powered down or
both channels can be set simultaneously by writing to the
channel index, Register 0x05[1:0].
Table 12. Low Power Modes
Mode
0x08[1:0]
Analog Circuitry
Clock
Ref
Normal
0x0
On
Power-Down
0x1
Off
On
Standby
0x2
Off
On
Sleep
0x3
Off
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