- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17022 > AD9278-50EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9278 PDF資料下載
參數(shù)資料
| 型號： | AD9278-50EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9278 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 8 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 10M ~ 50M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | * |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | * |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9278 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Data Sheet
AD9278
Rev. A | Page 37 of 44
SERIAL PORT INTERFACE (SPI)
The AD9278 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. The SPI
offers the user added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Three pins define the serial port interface, or SPI: SCLK, SDIO,
and CSB (see Table 17). The SCLK (serial clock) pin is used to
synchronize the read and write data presented to the device. The
SDIO (serial data input/output) pin is a dual-purpose pin that
allows data to be sent to and read from the internal memory map
registers of the device. The CSB (chip select bar) pin is an active
low control that enables or disables the read and write cycles.
Table 17. Serial Port Pins
Pin
Function
SCLK
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
Serial data input/output. Dual-purpose pin that
typically serves as an input or an output, depending
on the instruction sent and the relative position in
the timing frame.
CSB
Chip select bar (active low). This control gates the
read and write cycles.
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its defini-
tions can be found in Figure 66 and Table 18.
During normal operation, CSB is used to signal to the device
that SPI commands are to be received and processed. When
CSB is brought low, the device processes SCLK and SDIO to
execute instructions. Normally, CSB remains low until the
communication cycle is complete. However, if connected to a
slow device, CSB can be brought high between bytes, allowing
older microcontrollers enough time to transfer data into shift
registers. CSB can be stalled when transferring one, two, or three
bytes of data. When W0 and W1 are set to 11, the device enters
streaming mode and continues to process data, either reading
or writing, until CSB is taken high to end the communication
cycle. This allows complete memory transfers without the need
for additional instructions. Regardless of the mode, if CSB is taken
high in the middle of a byte transfer, the SPI state machine is
reset and the device waits for a new instruction.
In addition to the operation modes, the SPI port can be configured
to operate in different manners. For applications that do not
require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins in their secondary
mode, as defined in the SDIO Pin and SCLK Pin sections. CSB
can also be tied low to enable 2-wire mode. When CSB is tied
low, SCLK and SDIO are the only pins required for communication.
Although the device is synchronized during power-up, caution
must be exercised when using this mode to ensure that the
serial port remains synchronized with the CSB line. When
operating in 2-wire mode, it is recommended that a 1-, 2-, or
3-byte transfer be used exclusively. Without an active CSB line,
streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used to both program the chip and to read
the contents of the on-chip memory. If the instruction is a read-
back operation, performing a readback causes the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Data can be sent in MSB first mode or LSB first mode. MSB
first mode is the default at power-up and can be changed by
adjusting the configuration register. For more information
about this and other features, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 17 constitute the physical interface
between the user’s programming device and the serial port of
the AD9278. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, ensure that
pins that can be connected together and the resulting VOH level,
assuming the same load for each AD9278.
09424-
068
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0
30
20
10
40
50
60
70
80
90
100
Figure 65. SDIO Pin Loading
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9279-65EBZ | BOARD EVALUATION FOR AD9279 |
| AD9222-65EBZ | BOARD EVALUATION AD9222 65MSPS |
| CM453232-102KL | INDUCTR CHIP 1000UH 10% 1812 SMD |
| 1210R-681K | COIL .68UH IRON SMD |
| AD9212-65EBZ | BOARD EVALUATION FOR AD9212 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9278BBCZ | 功能描述:IC ADC 12BIT 50MSPS 144CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD9279 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator |
| AD9279-65EBZ | 功能描述:BOARD EVALUATION FOR AD9279 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9279-80KITZ | 功能描述:KIT EVALUATION FOR AD9279 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9279BBCZ | 功能描述:IC ADC 12BIT 80MSPS 144CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。