參數(shù)資料
型號： AD9278-50EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/44頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD9278
標準包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 12
采樣率（每秒）： 10M ~ 50M
數(shù)據(jù)接口： 串行
輸入范圍： *
在以下條件下的電源（標準）： *
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9278
已供物品： 板
AD9278
Data Sheet
Rev. A | Page 40 of 44
Table 19. AD9278 Memory Map Registers
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Comments
Chip Configuration Registers
0x00
CHIP_PORT_CONFIG
0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0
0x18
Nibbles should be
mirrored so that
LSB or MSB first
mode is set cor-
rectly regardless of
shift mode.
0x01
CHIP_ID
Chip ID Bits[7:0]
(AD9278 = 0x74), (default)
0x7D
Default is unique
chip ID, different
for each device.
Read-only register.
0x02
CHIP_GRADE
X
Speed Mode[5:4]
(identify device
variants of chip ID)
00: Mode I
(40 MSPS) (default)
01: Mode II (25 MSPS)
10: Mode III (50 MSPS)
11: Mode IV
(65 MSPS)
X
0x0X
Child ID used to
differentiate ADC
speed power
modes.
Device Index and Transfer Registers
0x04
DEVICE_INDEX_2
X
Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
E
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
0x05
DEVICE_INDEX_1
X
Clock
Channel
DCO±
1 = on
0 = off
(default)
Clock
Channel
FCO±
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
0xFF
DEVICE_UPDATE
X
SW
transfer
1 = on
0 = off
(default)
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Program Function Registers
0x08
Modes
X
0
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
0x00
Determines
generic modes
of chip operation
(global).
0x09
Clock
X
DCS
1 = on
(default)
0 = off
0x01
Turns the internal
duty cycle stabilizer
(DCS) on and off
(global).
0x0D
TEST_IO
User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
Reset PN
long
gen
1 = on
0 = off
(default)
Reset PN
short
gen
1 = on
0 = off
(default)
Output test mode—see
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by OUTPUT_MODE)
0x00
When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, expect
for PN sequence.)
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