參數(shù)資料
型號： AD9287ABCPZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 14/52頁
文件大?。?/td> 0K
描述： IC ADC 8BIT SRL 100MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 8
采樣率（每秒）： 100M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 562mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
Data Sheet
AD9287
Rev. E | Page 21 of 52
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9287 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 42 shows a preferred method for clocking the AD9287. The
low jitter clock source is converted from a single-ended signal to a
differential signal using an RF transformer. The back-to-back
Schottky diodes across the secondary transformer limit clock
excursions into the AD9287 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9287, and it preserves
the fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
CLK+
50
100
CLK–
CLK+
ADC
AD9287
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
05966-
024
Figure 42. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 43. The AD9510/
drivers offers excellent jitter performance.
10
0
0.1F
240
PECL DRIVER
CLK
CLK–
CLK+
ADC
AD9287
05966-
025
501
1
50 RESISTORS ARE OPTIONAL.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK+
CLK–
Figure 43. Differential PECL Sample Clock
10
0
0.1F
LVDS DRIVER
CLK
CLK–
CLK+
ADC
AD9287
05966-
026
50
1
50
1
150
RESISTORS ARE OPTIONAL.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK+
CLK–
Figure 44. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 k resistor (see Figure 45). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and
therefore offers several selections for the drive logic voltage.
0.1F
39k
CMOS DRIVER
50
1
OPTIONAL
100
0.1F
CLK
CLK–
CLK+
ADC
AD9287
05966-
027
150
RESISTORS ARE OPTIONAL.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK+
Figure 45. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CMOS DRIVER
OPTIONAL
100
CLK
0.1F
CLK–
CLK+
ADC
AD9287
05966-
028
50
1
150
RESISTORS ARE OPTIONAL.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK+
Figure 46. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals. As a result, these ADCs may be sensitive
to the clock duty cycle. Commonly, a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9287 contains a duty cycle stabilizer (DCS) that
retimes the nonsampling edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows a wide range of clock
input duty cycles without affecting the performance of the AD9287.
When the DCS is on, noise and distortion performance are nearly
flat for a wide range of duty cycles. However, some applications
may require the DCS function to be off. If so, keep in mind that
the dynamic range performance can be affected when operated
in this mode. See the Memory Map section for more details on
using this feature.
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 20 MHz
nominal. The loop has a time constant associated with it that
must be considered in applications where the clock rate can
change dynamically. This requires a wait time of 1.5 s to 5 s
after a dynamic clock frequency increase (or decrease) before
the DCS loop is relocked to the input signal. During the period
that the loop is not locked, the DCS loop is bypassed and the
internal device timing is dependent on the duty cycle of the input
clock signal. In such applications, it may be appropriate to disable
the duty cycle stabilizer. In all other applications, enabling the
DCS circuit is recommended to maximize ac performance.
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